71M6533 Datasheet, PDF(27/124 Page) Teridian Semiconductor Corporation

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

71M6533 Datasheet, PDF (27/124 Pages) Teridian Semiconductor Corporation – Energy Meter IC

◁

FDS_6533_6534_004

71M6533/71M6534 Data Sheet

transmission by the associated UART. Received data are available by reading from the receive buffer.

Both UARTs can simultaneously transmit and receive data.

WDCON[7] selects whether timer 1 or the internal baud rate generator is used. All UART transfers are

programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable commu-

nication baud rates from 300 to 38400 bps. Table 15 shows how the baud rates are calculated. Table 16

shows the selectable UART operation modes.

Table 15: Baud Rate Generation

UART0

UART1

Using Timer 1

(WDCON[7] = 0)

2smod * fCKMPU/ (384 * (256-TH1))

N/A

Using Internal Baud Rate Generator

(WDCON[7] = 1)

2smod * fCKMPU/(64 * (210-S0REL))

fCKMPU/(32 * (210-S1REL))

S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers.

SMOD is the SMOD bit in the SFR PCON register. TH1 is the high byte of timer 1.

Mode 0

Mode 1

Mode 2

Mode 3

Table 16: UART Modes

UART 0

N/A

Start bit, 8 data bits, stop bit, variable

baud rate (internal baud rate generator

or timer 1)

Start bit, 8 data bits, parity, stop bit,

fixed baud rate 1/32 or 1/64 of fCKMPU

Start bit, 8 data bits, parity, stop bit, va-

riable baud rate (internal baud rate ge-

nerator or timer 1)

UART 1

Start bit, 8 data bits, parity, stop bit, variable

baud rate (internal baud rate generator)

Start bit, 8 data bits, stop bit, variable baud

rate (internal baud rate generator)

N/A

Parity of serial data is available through the P flag of the accumulator. 7-bit serial modes with

parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of

8-bit output data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant

1. 8-bit serial modes with parity can be simulated by setting and reading the 9th bit, using the

control bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON and S1CON SFRs for transmit

and RB81 (S1CON[2]) for receive operations.

The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake sig-

nals for inter-processor communication in multi-processor systems. In this case, the slave processors

have bit SM20 (S0CON[5]) for UART0, or SM21 (S1CON[5] for UART1, set to 1. When the master proces-

sor outputs the slaveâs address, it sets the 9th bit to 1, causing a serial port receive interrupt in all the

slaves. The slave processors compare the received byte with their address. If there is a match, the ad-

dressed slave will clear SM20 or SM21 and receive the rest of the message. The rest of the slaveâs will

ignore the message. After addressing the slave, the host outputs the rest of the message with the 9th bit

set to 0, so no additional serial port receive interrupts will be generated.

UART Control Registers:

The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON

and S1CON shown in Table 17 and Table 18, respectively, and the PCON register shown in Table 19.

The UARTs require software to clear the interrupt bits. It is recommended to use bit manipulation instruc-

tions rather than byte instructions when using UART1 in full duplex mode. For example, the CLR TI0 in-

struction should be used instead of ANL #0FDH,S0CON. Further measures in code involve reducing and

combining the write operations to S1CON and reducing the time between the read and write operations on

v1.1

▷