71M6521BE Datasheet, PDF (75/97 Pages) Teridian Semiconductor Corporation – Energy Meter IC

TMUX[4:0]
VERSION[7:0]
VREF_CAL
VREF_DIS
WAKE_ARM
WAKE_PRD
WAKE_RES
WD_RST
WD_OVF
71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
20AA[4:0] 2 -- R/W Selects one of 32 signals for TMUXOUT.
[4:0] Selected Signal
[4:0] Selected Signal
0x00 DGND (analog)
0x01 Reserved
0x02 Reserved
0x03 Reserved
0x04 Reserved
0x05 Reserved
0x06 VBIAS (analog)
0x07 Not used
0x08 Reserved
0x09 Reserved
0x0A Reserved
0x0B Reserved
-0x13
0x14
RTM (Real time
output from CE)
0x15 WDTR_E, comparator 1
Output AND V1LT3)
0x16 – Not used
0x17
0x18
RXD, from optical in-
terface, after optional
inversion
0x19 MUX_SYNC
0x1A CK_10M
0x1B CK_MPU
0x1C Reserved
0x1D Reserved
0x1E CE_BUSY
0x1F XFER_BUSY
2006
-- --
R The version index. This word may be read by firmware to determine
the silicon version.
VERSION[7:0] Silicon Version
0000 0110
A06
2004[7]
2004[3]
0 0 R/W Brings VREF to VREF pad. This feature is disabled when
VREF_DIS=1.
0 1 R/W Disables the internal voltage reference.
20A9[7]
0 -- W Arm the autowake timer. Writing a 1 to this bit arms the autowake
timer and presets it with the values presently in WAKE_PRD and
WAKE_RES. The autowake timer is reset and disarmed whenever
the processor is in MISSION mode or BROWNOUT mode. The
timer must be armed at least three crystal clock cycles before the
SLEEP or LCD-ONLY mode is commanded.
20A9[2:0] 001 -- R/W Sleep time. Time=WAKE_PRD[2:0]*WAKE_RES. Default=001.
Maximum value is 7.
20A9[3]
0 -- R/W Resolution of WAKE timer: 1 – 1 minute, 0 – 2.5 seconds.
SFRE8[7] 0 0 W WD timer bit: Possible operations to this bit are:
Read: Gets the status of the flag IE_PLLFALL
Write 0: Clears the flag
Write 1:.Resets the WDT
2002[2]
0 0 R/W The WD overflow status bit. This bit is set when the WD timer
overflows. It is powered by the nonvolatile supply and at bootup will
indicate if the part is recovering from a WD overflow or a power fault.
This bit should be cleared by the MPU on bootup. It is also
automatically cleared when RESET is high.
V1.0
© 2005-2008 TERIDIAN Semiconductor Corporation
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