71M6521BE Datasheet, PDF (74/97 Pages) Teridian Semiconductor Corporation – Energy Meter IC

71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
OPT_FDC[1:0]
OPT_RXDIS
OPT_RXINV
OPT_TXE[1,0]
OPT_TXINV
OPT_TXMOD
PLL_OK
PLS_MAXWIDTH
[7:0]
PLS_INTERVAL
[7:0]
PLS_INV
PREBOOT
PRE_SAMPS[1:0]
RTM_E
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
SECURE
SLEEP
SUM_CYCLES[5:0]
2007[1:0]
2008[5]
2008[4]
2007[7,6]
2008[0]
2008[1]
2003[6]
2080[7:0]
2081[7:0]
2004[6]
SFRB2[7]
2001[7:6]
2002[3]
2060
2061
2062
2063
SFRB2[6]
20A9[6]
2001[5:0]
0 0 R/W Selects OPT_TX modulation duty cycle
OPT_FDC Function
00
50% Low
01
25% Low
10
12.5% Low
11
6.25% Low
0 0 R/W OPT_RX can be configured as an analog input to the optical UART
comparator or as a digital input/output, DIO1.
0—OPT_RX, 1—DIO1.
0 0 R/W Inverts result from OPT_RX comparator when 1. Affects only the
UART input. Has no effect when OPT_RX is used as a DIO input.
00 00 R/W Configures the OPT_TX output pin.
00—OPT_TX, 01—DIO2, 10—WPULSE, 11—RESERVED
0 0 R/W Invert OPT_TX when 1. This inversion occurs before modulation.
0 0 R/W Enables modulation of OPT_TX. When OPT_TXMOD is set,
OPT_TX is modulated when it would otherwise have been zero.
The modulation is applied after any inversion caused by
OPT_TXINV.
00
R Indicates that system power is present and the clock generation PLL
is settled.
FF FF R/W Determines the maximum width of the pulse (low going pulse).
Maximum pulse width is (2*PLS_MAXWIDTH + 1)*T_I. Where T_I is
PLS_INTERVAL. If PLS_INTERVAL=0, T_I is the sample time
(397µs). If 255, disable MAXWIDTH.
0 0 R/W If the FIFO is used, PLS_INTERVAL must be set to 81. If
PLS_INTERVAL = 0, the FIFO is not used and pulses are output as
soon as the CE issues them.
0 0 R/W Inverts the polarity of WPULSE. Normally, these pulses are active
low. When inverted, they become active high.
-- --
R Indicates that preboot sequence is active.
0
0
R/W
The duration of the pre-summer, in samples.
00-42, 01-50, 10-84, 11-100.
0 0 R/W Real Time Monitor enable. When ‘0’, the RTM output is low. This bit
enables the two wire version of RTM
0 0 R/W Four RTM probes. Before each CE code pass, the values of these
00
registers are serially output on the RTM pin. The RTM registers are
00
ignored when RTM_E=0.
00
0 -- R/W Enables security provisions that prevent external reading of flash
memory and CE program RAM. This bit is reset on chip reset and
may only be set. Attempts to write zero are ignored.
0 0 W Takes the 6521BE to sleep mode. Ignored if system power is
present. The 6521BE will wake when the autowake timer times out,
when push button is pushed, or when system power returns.
0 0 R/W The number of pre-summer outputs summed in the final summer.
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