71M6521BE Datasheet, PDF (16/97 Pages) Teridian Semiconductor Corporation – Energy Meter IC

71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
80515 MPU Core
The 71M6521BE includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a
5MHz clock results in a processing throughput of 5 MIPS. The 80515 architecture eliminates redundant bus states and im-
plements parallel execution of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, there-
fore, most of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (in average) improvement
(in terms of MIPS) over the Intel 8051 device running at the same clock frequency.
Actual processor clocking speed can be adjusted to the total processing demand of the application (metering calculations,
AMR management, memory management, LCD driver management and I/O management) using the I/O RAM register
MPU_DIV[2:0].
Typical measurement and metering functions based on the results provided by the internal 32-bit compute engine (CE) are
available for the MPU as part of TERIDIAN’s standard library. A standard ANSI “C” 80515-application programming interface
library is available to help reduce design cycle.
Memory Organization
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.
Memory organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas: Program
memory (Flash), external data memory (XRAM), physically consisting of XRAM, CE DRAM, and I/O RAM, and internal data
memory (Internal RAM). Table 3 shows the memory map.
Address
(hex)
0000-1FFF
on 1K
boundary
0000-07FF
1000-11FF
2000-20FF
Memory
Technology
Flash Memory
Flash Memory
Static RAM
Static RAM
Static RAM
Memory Type
Typical Usage
Non-volatile
Non-volatile
MPU Program and non-
volatile data
CE program
Volatile
Volatile
Volatile
MPU data XRAM,
CE data
Configuration RAM
I/O RAM
Table 3: Memory Map
Wait States
(at 5MHz)
0
0
0
6
0
Memory Size
(bytes)
8K
2K
2K
512
256
Internal and External Data Memory: Both internal and external data memory are physically located on the 71M6521BE IC.
“External” data memory is only external to the 80515 MPU core.
Program Memory: The 80515 can theoretically address up to 64KB of program memory space from 0x0000 to 0xFFFF.
Program memory is read when the MPU fetches instructions or performs a MOVC operation.
After reset, the MPU starts program execution from location 0x0000. The lower part of the program memory includes reset and
interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting from 0x0003.
External Data Memory: While the 80515 is capable of addressing up to 64KB of external data memory in the space from
0x0000 to 0xFFFF, only the memory ranges shown in Error! Reference source not found. contain physical memory. The
80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU
reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR instruction (SFR USR2 provides the upper 8
bytes for the MOVX A,@Ri instruction).
Clock Stretching: MOVX instructions can access fast or slow external RAM and external peripherals. The three low order bits
of the CKCON register define the stretch memory cycles. Setting all the CKCON stretch bits to one allows access to very slow
external RAM or external peripherals.
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© 2005-2008 TERIDIAN Semiconductor Corporation
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