71M6521BE Datasheet, PDF (25/97 Pages) Teridian Semiconductor Corporation – Energy Meter IC

71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter or timer
operations.
In timer mode, the register is incremented every machine cycle meaning that it counts up after every 12 periods of the MPU
clock signal.
In counter mode, the register is incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0
and T1 are the timer gating inputs derived from certain DIO pins, see the DIO Ports chapter). Since it takes two machine
cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator frequency. There are no restrictions on
the duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle.
The timers/counters are controlled by the TCON Register
Timer/Counter Control Register (TCON)
MSB
LSB
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Table 18: The TCON Register
Bit
TCON.7
TCON.6
TCON.5
TCON.4
TCON.3
TCON.2
TCON.1
TCON.0
Symbol
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Function
The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag
can be cleared by software and is automatically cleared when an interrupt is
processed.
Timer 1 Run control bit. If cleared, Timer 1 stops.
Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can be
cleared by software and is automatically cleared when an interrupt is processed.
Timer 0 Run control bit. If cleared, Timer 0 stops.
Interrupt 1 edge flag is set by hardware when the falling edge on external pin
int1 is observed. Cleared when an interrupt is processed.
Interrupt 1 type control bit. Selects either the falling edge or low level on input
pin to cause an interrupt.
Interrupt 0 edge flag is set by hardware when the falling edge on external pin
int0 is observed. Cleared when an interrupt is processed.
Interrupt 0 type control bit. Selects either the falling edge or low level on input
pin to cause interrupt.
Table 19: The TCON Register Bit Functions
V1.0
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