RM0316 Datasheet, PDF (971/1141 Pages) STMicroelectronics – This reference manual targets application developers

RM0316
Serial peripheral interface / inter-IC sound (SPI/I2S)
RXFIFO threshold is set to 16 bits (FRXTH=0). The receiver then has to access both data
frames by a single 16-bit read of SPIx_DR as a response to this single RXNE event. The
RxFIFO threshold setting and the following read access must be always kept aligned at the
receiver side, as data can be lost if it is not in line.
A specific problem appears if an odd number of such “fit into one byte” data frames must be
handled. On the transmitter side, writing the last data frame of any odd sequence with an 8-
bit access to SPIx_DR is enough. The receiver has to change the Rx_FIFO threshold level
for the last data frame received in the odd sequence of frames in order to generate the
RXNE event.
Figure 356. Packing data in FIFO for transmission and reception
166
63,[B'5
[ [$
7;),)2
[$
[
6&.
026,
63,IVP
VKLIW
[$
[
63,IVP
VKLIW
5;),)2
[$
[
63,[B'5
[ [$
ELWDFFHVVZKHQZULWHWRGDWDUHJLVWHU
63,B'5 [$ZKHQ7[( 
ELWDFFHVVZKHQUHDGIURPGDWDUHJLVWHU
63,B'5 [$ZKHQ5[1( 
069
Communication using DMA (direct memory addressing)
To operate at its maximum speed and to facilitate the data register read/write process
required to avoid overrun, the SPI features a DMA capability, which implements a simple
request/acknowledge protocol.
A DMA access is requested when the TXE or RXNE enable bit in the SPIx_CR2 register is
set. Separate requests must be issued to the Tx and Rx buffers.
• In transmission, a DMA request is issued each time TXE is set to 1. The DMA then
writes to the SPIx_DR register.
• In reception, a DMA request is issued each time RXNE is set to 1. The DMA then reads
the SPIx_DR register.
See Figure 357 through Figure 360.
When the SPI is used only to transmit data, it is possible to enable only the SPI Tx DMA
channel. In this case, the OVR flag is set because the data received is not read. When the
SPI is used only to receive data, it is possible to enable only the SPI Rx DMA channel.
In transmission mode, when the DMA has written all the data to be transmitted (the TCIF
flag is set in the DMA_ISR register), the BSY flag can be monitored to ensure that the SPI
communication is complete. This is required to avoid corrupting the last transmission before
disabling the SPI or entering the Stop mode. The software must first wait until
FTLVL[1:0]=00 and then until BSY=0.
When starting communication using DMA, to prevent DMA channel management raising
error events, these steps must be followed in order:
DocID022558 Rev 5
971/1141
1014