RM0316 Datasheet, PDF (766/1141 Pages) STMicroelectronics – This reference manual targets application developers

Independent watchdog (IWDG)
RM0316
25.3.4
25.3.5
Register access protection
Write access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers is protected. To
modify them, you must first write the code 0x0000 5555 in the IWDG_KR register. A write
access to this register with a different value will break the sequence and register access will
be protected again. This implies that it is the case of the reload operation
(writing 0x0000 AAAA).
A status register is available to indicate that an update of the prescaler or the down-counter
reload value or the window value is on going.
Debug mode
When the microcontroller enters debug mode (core halted), the IWDG counter either
continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in
DBG module. For more details, refer to Section 33.16.2: Debug support for timers,
watchdog, bxCAN and I2C
25.4
25.4.1
IWDG registers
Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
Key register (IWDG_KR)
Address offset: 0x00
Reset value: 0x0000 0000 (reset by Standby mode)
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
Res.
24
Res.
23
Res.
22
Res.
21
Res.
20
Res.
19
Res.
18
Res.
17
Res.
16
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
KEY[15:0]
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 KEY[15:0]: Key value (write only, read 0x0000)
These bits must be written by software at regular intervals with the key value 0xAAAA,
otherwise the watchdog generates a reset when the counter reaches 0.
Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and
IWDG_WINR registers (see Section 25.3.4: Register access protection)
Writing the key value CCCCh starts the watchdog (except if the hardware watchdog option is
selected)
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