RM0316 Datasheet, PDF (104/1141 Pages) STMicroelectronics – This reference manual targets application developers

Power control (PWR)
RM0316
If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB
access is finished.
In Stop mode, the following features can be selected by programming individual control bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 25.3: IWDG functional description in Section 25: Independent watchdog
(IWDG).
• real-time clock (RTC): this is configured by the RTCEN bit in the RTC domain control
register (RCC_BDCR)
• Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
RTC domain control register (RCC_BDCR).
The ADC or DAC can also consume power during the Stop mode, unless they are disabled
before entering it. To disable the ADC, the ADDIS bit must be set in the ADCx_CR register.
To disable the DAC, the ENx bit in the DAC_CR register must be written to 0.
Exiting Stop mode
Refer to Table 19 for more details on how to exit Stop mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is
selected as system clock.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop
mode, the consumption is higher although the startup time is reduced.
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