RM0316 Datasheet, PDF (173/1141 Pages) STMicroelectronics – This reference manual targets application developers

RM0316
Flexible memory controller (FMC)
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Figure 19. FMC memory banks
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10.4.1
NOR/PSRAM address mapping
HADDR[27:26] bits are used to select one of the four memory banks as shown in Table 33.
Table 33. NOR/PSRAM bank selection
HADDR[27:26]⁽¹⁾
Selected bank
00
Bank 1 - NOR/PSRAM 1
01
Bank 1 - NOR/PSRAM 2
10
Bank 1 - NOR/PSRAM 3
11
Bank 1 - NOR/PSRAM 4
1. HADDR are internal AHB address lines that are translated to external memory.
The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte
address whereas the memory is addressed at word level, the address actually issued to the
memory varies according to the memory data width, as shown in the following table.
Table 34. NOR/PSRAM External memory address
Memory width⁽¹⁾ Data address issued to the memory Maximum memory capacity (bits)
8-bit
16-bit
HADDR[25:0]
HADDR[25:1] >> 1
64 Mbytes x 8 = 512 Mbit
64 Mbytes/2 x 16 = 512 Mbit
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