RM0316 Datasheet, PDF (192/1141 Pages) STMicroelectronics – This reference manual targets application developers

Flexible memory controller (FMC)
RM0316
The differences with mode1 are the toggling of NOE that goes on toggling after NADV
changes and the independent read and write timings.
Bit No.
31-21
20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
3-2
1
0
Table 54. FMC_BCRx bit fields
Bit name
Value to set
Reserved
0x000
CCLKEN
As needed
CBURSTRW
Reserved
0x0 (no effect in asynchronous mode)
0x0
ASYNCWAIT
EXTMOD
Set to 1 if the memory supports this feature. Otherwise keep
at 0.
0x1
WAITEN
0x0 (no effect in asynchronous mode)
WREN
As needed
WAITCFG
WRAPMOD
WAITPOL
Don’t care
0x0
Meaningful only if bit 15 is 1
BURSTEN
0x0
Reserved
0x1
FACCEN
MWID
Set according to memory support
As needed
MTYP
As needed
MUXEN
0x0
MBKEN
0x1
Bit No.
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Bit name
Reserved
ACCMOD
DATLAT
CLKDIV
BUSTURN
DATAST
ADDHLD
ADDSET
Table 55. FMC_BTRx bit fields
Value to set
0x0
0x3
Don’t care
Don’t care
Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST HCLK cycles) for
read accesses.
Duration of the middle phase of the read access (ADDHLD HCLK
cycles)
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses. Minimum value for ADDSET is 1.
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