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| RM0316 Datasheet, PDF (273/1141 Pages) STMicroelectronics – This reference manual targets application developers | |||
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RM0316
Direct memory access controller (DMA)
SYSCFG configuration register 3 (SYSCFG_CFGR3) on page 257.
2. SPI1_TX_DMA_RMP[1:0] bits in SYSCFG configuration register 2 (SYSCFG_CFGR2) allow remapping of
SPI1_TX on channel 5 and 7.
Table 77. STM32F303xB/C/D/E, STM32F358xC and STM32F398xE summary of DMA1 requests
for each channel
Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel6 Channel7
ADC
SPI
USART
I2C
ADC1
I2C3_TX(1)
TIM1
TIM2
TIM2_CH3
TIM3
TIM4
TIM4_CH1
TIM6 / DAC
TIM7/DAC
SPI1_RX
SP1_TX
SPI2_RX
USART3_
TX
I2C3_RX(1)
USART3_RX
USART1_
TX
I2C2_TX
TIM1_CH1
TIM1_CH2
TIM1_CH4
TIM1_TRIG
TIM1_COM
TIM2_UP
TIM3_CH3
TIM3_CH4
TIM3_UP
TIM6_UP
DAC_CH1 (2)
TIM4_CH2
TIM7_UP
DAC_CH2
(2)
SPI2_TX
USART1_
RX
I2C2_RX
USART2_RX USART2_TX
I2C1_TX I2C1_RX
TIM1_UP TIM1_CH3
TIM2_CH1
TIM4_CH3
TIM3_CH1
TIM3_TRIG
TIM2_CH2
TIM2_CH4
TIM4_UP
TIM15
TIM16
TIM16_CH1
TIM16_UP
TIM15_CH1
TIM15_UP
TIM15_TRIG
TIM15_COM
TIM16_CH1
TIM16_UP
(2)
TIM17
TIM17_CH1
TIM17_UP
TIM17_CH1
TIM17_UP(2)
1. Available in STM32F303xD/E only.
2. DMA request mapped on this DMA channel only if the corresponding remapping bit is set in the SYSCFG_CFGR1 register.
For more details, please refer to Section 12.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1) on page 245.
Table 78. STM32F303x6/8 and STM32F328x8 summary of DMA1 requests
for each channel
Peripheral Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel6 Channel7
ADC
SPI
ADC1
ADC2
SPI1_RX
SP1_TX
ADC2(1)
SPI1_RX(1)
SPI1_TX(1)
SPI1_RX(1) SPI1_TX(1)
USART
I2C
USART3
_TX
I2C1_TX(1)
USART3
_RX
I2C1_RX(1)
USART1_TX
I2C1_TX(1)
USART1
_RX
I2C1_RX(1)
USART2
_RX
I2C1_TX
USART2_TX
I2C1_RX
DocID022558 Rev 5
273/1141
284
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