EF9345 Datasheet, PDF (6/38 Pages) STMicroelectronics – HMOS2 SINGLE CHIP SEMI-GRAPHIC DISPLAY PROCESSOR

EF9345
MICROPROCESSOR INTERFACE
EF9345 is motel compatible. It automatically se-
lects the processor type by using AS input latch to
state of the DS input.
No external logic is needed to adapt bus control
signals from most of the common multiplexed bus
microprocessors.
EF9345
AS
DS
R/W
6801
Timing 1
AS
DS, E, φ 2
R/W
INTEL Family
Timing 2
ALE
RD
WR
MICROPROCESSOR INTERFACE TIMING AD(0:7), AS, DS, R/W, CS
VCC = 5.0V ±5%, TA = 0 to + 70°C, CL = 100pF on AD(0:7)
Reference Levels : VIL = 0.8V and VIH = 2V on All Inputs ; VOL = 0.4V and VOH on all Outputs.
Symbol Ident. N°
Parameter
Min. Typ. Max. Unit
t_CYC
1
Memory Cycle Time
t_ASD
2
DS Low to AS High (Timing 1)
DS High or R/W High to AS High (Timing 2)
400
ns
30
ns
t_ASED
3
AS Low to High (Timing 1)
AS Low to DS Low or R/W Low (Timing 2)
30
ns
tPWEH
tPWASH
t_RWS
tRWH
t_ASL
tAHL
t_DSW
t_DHW
t_DDR
tDHR
tACC
4
Write Pulse Width
5
AS Pulse Width
6
R/W to DS Setup Time (Timing 1)
7
R/W to DS Hold Time (Timing 1)
8
Address and CS Setup Time
9
Address and CS Hold Time
10 Data Setup Time (Write Cycle)
11 Data Hold Time (Write Cycle)
12 Data Access Time from DS (Read Cycle)
13 DS Inactive to High Impedance State Time (Read Cycle)
14 Address to Data Valid Access Time
200
ns
100
ns
100
ns
10
ns
20
ns
20
ns
100
ns
10
ns
150 ns
10
80 ns
300 ns
Figure 3 : Microprocessor Interface Timing Diagram 1 (6801 Type)
1
2
2
3
DS
ASM
5
6
7
R/W
CS
WRITE CYCLE
AD (0:7)
READ CYCLE
AD (0:7)
8
9
ADDRESS
8
9
12
ADDRESS
14
10
INPUT DATA
OUTPUT
DATA
11
13
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