EF9345 Datasheet, PDF (12/38 Pages) STMicroelectronics – HMOS2 SINGLE CHIP SEMI-GRAPHIC DISPLAY PROCESSOR

EF9345
Data Structure in Memory
A page is a data structure displayable on the
screen up to 25 rows of characters. According to
the character code format, each row on the screen
is associated with 2 (or 3) 40-byte buffers. This set
of 2 (or 3) buffers constitutes a row buffer (Fig-
ure 8). The buffers belonging to a row buffer must
meet the following requirements :
- They have the same Y address,
- They have the same district number,
- They lie at 2 (or 3) successive (modulo 4) block
addresses in their common district.
Consequently, a row buffer is defined by its first
buffer address and its format.
A page is a set of successive row buffers :
- With the same format,
- With the same district number,
- With the same block address of first buffer. This
block address must be even,
- Lying at successive (modulo 24) Y addresses.
Figure 10 : Memory Cycle Allocation
Consequently, a page should not cross a district
boundary. General purpose memory area may be
used but should respect the buffer of row buffer
structure. See Figure 9 for pointer incrementation
implied by these data structures.
Memory Time Sharing (See Figure 10)
The memory interface provides a 500 ns cycle time.
That is to say a 2 Mbyte/s memory bandwith. This
bandwith is shared between :
- Reading a row buffer from memory to load the
internalrow buffer(up to 120 bytes once each row),
- Reading user defined characters slices from me-
mory (1 byte each µs),
- Indirect microprocessor read or write operation,
- Refresh cycles to allow DRAM use, with no over-
head.
A fixed allocation scheme implements the sharing.
During these lines, no microprocessor access is
provided for 104µs ; this hold too when no user
defined character slices are addressed.
40µs
24µs
312/362
SCAN
LINES
250/210
ACTIVE
SCAN
LINES
ACTIVE
DISPLAY
TIME
ONE ROW = 10 SCAN LINES
INACTIVE LINE
LAST ROW LINE
FIRST ROW LINE
OTHER ROW LINE
DUM µP
UDS LD
UDS LD
UDS µP
1µs
40µs
RFSH µP
LD LD
RFSH µP
RFSH µP
1µs
24µs
MEMORY CYCLE
DUM : dummy cycle
µP : indirect access to memory
RFSH : refresh cycle
UDS : slice read cycle
LD : read cycle to load the internal row buffer
Notes : 1.
2.
3.
Dummy cycles are read cycles at dummy addresses.
RFSH cycles are read cycles performed by an 8-bit auto-incrementing counter. Low order address byte ADM(0:7) cycles
through its 256 states in less than 1ms.
The microprocessor may indirectly access the memory once every µs, except during the first and the last line of a row, when
the internal buffer must be reloaded.
Figure 11 : Logical to Physical Address Transcoding Performed On-chip
Z (0 to 15)
D
B
Y (0, 1 ; 8 to 31)
X (0 to 39)
LOGICAL
ADDRESS
3
2
1
0
43210
543210
TRANSCODING
PHYSICAL
ADDRESS
13 12 11
10 9 8 7 6 5 4 3
210
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