EF9345 Datasheet, PDF (34/38 Pages) STMicroelectronics – HMOS2 SINGLE CHIP SEMI-GRAPHIC DISPLAY PROCESSOR

EF9345
Data Phase - Registers
When EF9345 isselected and while AS input is low,
the Ri register is accessed.
R0 designates a write-only COMMAND register or
a read-only STATUS register.
R1 to R7 hold the arguments of a command. They
are read/write registers.
R1, R2, R3 are used to transfer the data.
R4, R5 hold the Auxiliary Pointer (AP).
R6, R7 hold the Main Pointer (MP).
(see memory organization ; pinter section for
pointer structure).
Command Register
This register holds a 4-bit command type and 4 bits
of orthogonal parameters (see command table).
Type
There are 4 groups of command :
The IND command which gives access to on-chip
resources,
The fixed format character code transfer com-
mands,
The variable character code handling commands,
The general purpose commands.
Parameters
R/W : Direction
1 : to DATA registers (R1, R2, R3)
0 : from DATA registers.
r:
Internal resource index (see figure 27).
l:
Auto-incrementation
1 : with post auto-incrementation
0 : without auto-incrementation
Figure 37 : Indirect On-Chip Resource Access
p:
s, s :
a, a :
Pointer select
1 : auxiliary pointer
0 : main pointer
Source, destination select
01 : source : MP ; destination : AP
10 : source : AP ; destination : MP
Stop condition
01 : stop at end of buffer
10 : no stop.
Status Register
This is a read-only, direct access register.
S7 : BUSY BUSY is set at the beginningof any
command execution. It is reset at
completion.
S6 : AI
S5 LXm
S4 : _LXa
LXm or LXa is set when res-
pectively the main pointer or the
auxiliary pointer holds X = 39
before a possible incrementation.
The alarm bit S6 is set when LXm
or LXa is set and an incrementation
is performed after access.
S3 :
Gives the MSB value of R1.
S2 :
Gives the vertical synchronization
signal state.
This is maskable by the VRM
command.
S1 = S0 = 0 Not used.
S3 to S6 are reset at the beginning of any com-
mand.
The COMMAND TABLE shows every command
able to set, each of these status bits, after comple-
tion.
76543210
1 0 0 0 R/W
r
IND
COMMAND
R1 ^X
R2 ^-
R3
R4 -
R5 -
R6 -
R7 -
r Register
0 ROM*
1
TGS
2
MAT
3
PAT
4
DOR
5
6
7
ROR
* A slice in 400 only can be read from the internal
character generator.
The slice address must be initialized in R6, R7.
R6 ... B6 C6 C5 C4 C3 C2
NT
R7 B4 B5 3 2 1 0 C₁ C₀
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