EF9345 Datasheet, PDF (5/38 Pages) STMicroelectronics – HMOS2 SINGLE CHIP SEMI-GRAPHIC DISPLAY PROCESSOR

EF9345
MEMORY INTERFACE
VCC = 5.0V ±5%, TA = 0 to + 70°C
Clock : fin = 12MHz ; Duty Cycle 40 to 60% ; tr, tf < 5ns
Reference Levels : V_IL = 0.8V and V_IH = 2V, V_OL = 0.4V and V_OH = 2.4V
Symbol
tELEL
t_D
t_EHEL
tELDV
tDA
t_AVEL
t_ELAX
tCLAZ
tGHDX
t_OZ
t_GLDV
t_QVWL
tWHQX
tWLWH
Ident. N°
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Parameter
Memory Cycle Time
Output Delay Time from CLK Rising Edge (ASM, OE, WE)
ASM High Pule Width
Memory Access Time from ASM Low
Output Delay Time from CLK Rising Edge (ADM(0:7), AM(8:13))
Address Setup Time to ASM
Address Hold Time from ASM
Address Off Time
Memory Hold Time
Data Off Time from OE
Memory OE Access Time
Data Setup Time (Write Cycle)
Data Hold Time (Write Cycle)
WE Pulse Width
Min. Typ. Max. Unit
500
ns
60 ns
120
ns
290 ns
80 ns
30
ns
55
ns
80 ns
10
ns
60 ns
150 ns
30
ns
30
ns
110
ns
Figure 1 : Test Load
V_DD
Test
Point
C_L
R_L
MMD7000
R
or equivalent
Table 1
Symbol
C
R_L
R
AM(8:13)
ADM(0:7)
AD(0:7)
100pF
1kΩ
4.7kΩ
Other
Outputs
50pF
3.3kΩ
4.7kΩ
Figure 2 : Memory Interface Timing Diagram
T
1
CLK
2
ASM
4
2
56
8
7
3
5
56
7
ADM (0:7)
READ ADDRESS
D _IN
WRITE ADDRESS
AM (8:14)
OE
WE
2
2
9
11
10
12
D _OUT
2
2
14
13
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