EF9345 Datasheet, PDF (2/38 Pages) STMicroelectronics – HMOS2 SINGLE CHIP SEMI-GRAPHIC DISPLAY PROCESSOR

EF9345
PIN DESCRIPTION (All the input/output pins are TTL compatible)
Name
Pin
Type
Pin N°
Function
Description
MICROPROCESSOR INTERFACE
AD(0:7)
I/O
17-29
21-25
Multiplexed
Address/Data
Bus
AS
I
14
Address
Strobe
DS
I
15
Data Strobe
R/W
I
16
CS
I
26
MEMORY INTERFACE
Read/Write
Chip Select
These 8 bidirectional pins provide communication with the
microprocessor system bus.
The falling edge of this control signal latches the address on the
AD(0:7) lines, the state of the Data Strobe (DS) and Chip Select (CS)
into the chip.
When this input is strobed high by AS, the output buffers are selected
while DS is low for a read cycle (R/W = 1).
In write cycle, data present on AD(0:7) lines are strobed by R/W low
(see timing diagram 2).
When this input is strobed low by AS, R/W gives the direction of data
transfer on AD(0:7) bus. DS high strobes the data to be written during
a write cycle (R/W = 0) or enables the output buffers during a read
cycle (R/W = 1). (see timing diagram 1).
This input determines whether the Internal registers get written or
read. A write is active low (”O”).
The EF9345 is selected when this input is strobed low by AS.
ADM(0:7) I/O
AM(8:13) O
OE
O
WE
O
ASM
O
40-43
32-27
2
3
4
Multiplexed
Address/Data
Bus
Memory
Address Bus
Output Enable
Write Enable
Memory
Address
Strobe
Lower 8 bits of memory address appear on the bus when ASM is
high. It then becomes the data bus when ASM is low.
These 6 pins provide the high order bits of the memory address.
When low, this output selects the memory data output buffers.
This output determines whether the memory gets read or written. A
write is active low (”0”).
This signal cycles continuously. Address can be latched on its falling
edge.
OTHER PINS
CLK
I
12
VSS
S
1
V_CC
S
20
VIDEO INTERFACE
R
O
7
G
O
8
B
O
9
I
O
10
HVS/HS O
5
PC/VS
O
6
SYNC IN I
13
HP
O
11
Clock Input
Power Supply
Power Supply
External TTL clock Input (nominal value : 12MHz, duty cycle : 50%).
Ground.
+5V
Red
Green
Blue
Insert
Sync. Out
Phase
Comparator /
Vertical Sync
Synchro In
Video Clock
These outputs deliver the video signal. They are low during the
vertical and horizontal blanking intervals.
This active high output allows to insert R : G: B : in an external video
signal for captioning purposes, for example. It can also be used as a
general purpose attribute or color.
This output delivers either the composite synchro (bit TGS₄ = 1) or the
horizontal synchro signal (bit TGS4 = 0)
When TGS₄ = 1, this signal is the phase comparator output.
When TGS₄ = 0, this output delivers the vertical synchro signal.
This input allows vertical and/or horizontal synchronizing the EF9345
on an external signal. It must be grounded if not used.
This output delivers a 4MHz clock phased with the R, G, B, I signals.
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