EF9345 Datasheet, PDF (14/38 Pages) STMicroelectronics – HMOS2 SINGLE CHIP SEMI-GRAPHIC DISPLAY PROCESSOR

EF9345
Insert Modes : PAT(4:5)
During retrace, margin and extended margin peri-
ods, the I output pin delivers the value of the insert
margin attribute.
I = IM = MAT4
During active line period, the I output state is con-
trolled by the Insert Mode and i, the insert attribute
of each character. The I output pin may have
several uses (see Figure 12) :
- As a margin/active area signal in the active area
mark mode.
- As a character per character marker signal in the
character mark mode.
- As a video mixing signal in the two remaining
modes, provided that the EF9345 has been ver-
tically and horizontally synchronized with an ex-
ternal video source : the I pin allows mixing RGB
outputs (I = 1) and the external video signal
(I = 0). This mixing can be achieve by switching
or Oring. It may occur for the complete character
window (Boxing Mode) or only for the foreground
pixels (Inlay Mode).
Table 3 : Video Outputs During Active Periods
Insert Mode
Char. Level
i Pixels ⁽¹⁾
Outputs
I
R, G, B
(2)
Active Area Mark
Character Mark
Boxing
Inlay
–
1
X
0
–
0
X
1
–
1
X
0
–
0 BLACK
1
–
1
X
0
–
0 BLACK
1 BACKGND 0 BLACK
FOREGND 1
X
Notes : 1.
2.
Pixel type :
– : Dont’t care.
FOREGRND = A foreground pixel is :
- Any pixel of a quadrichrome cha racter,
- A pixel of a bichrome character ge nerated from a ”1” in the
character generator cell.
RGB outputs :
X : Not affected.
BLACK : Forced to low level.
Timing Generator Options : TGS(0:4)
TGS(0:1) select the number of lines per frame :
TGS₁
0
0
1
1
TGS₀
0
1
0
1
LINES
312
262
312.5
262.5
NON INTERLACED
INTERLACED
The composite incoming SYNC IN signal is sepa-
rated into 2 internals signals :
- Vertical Synchronization In (VSI),
- Horizontal Synchronization In (HSI).
TGS3 enable VSI to reset the internal line count.
SYNC IN input is sampled at the beginning of the
active area of each line. When the sample transits
from 1 to 0, the line count is reset at the end of the
current line.
TGS₂ enables HSI to control an internal digital
phase lock loop. HSI and on-chip generated HS
Out are considered as in phase if their leading
edges match at ±1 clock period.
When they are out of phase, the line period is
lengthened by 1 clock period (≈80ns).
TGS4 controls the SYNC OUT pins configuration :
TGS4
1
0
HVS / HS
Composite Sync
H Sync Out
PC / VS
PC
V Sync Out
PC is the output of the on-chip phase comparator.
An external VCXO allows a smoother horizontal
phase lock than the internal scheme.
Figure 12
SYNC IN
HVS/HS
CLK
DQ
PC
DQ
HS
VS
÷6
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