STM32W108C8 Datasheet, PDF (49/275 Pages) –

STM32W108C8
System modules
6.2.4
Reset register
Reset status register (RST_SR)
Address offset: 0x4000 002C
Reset value: 0x0000 0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
Reserved
8
7
6
5
4
3
2
1
0
LKUP OBFAIL WKUP SWRST WDG PIN PWRLV PWRHV
r
r
r
r
r
r
r
r
Bits 31:8 Reserved, must be kept at reset value
Bit 7 LKUP:
When set to ‘1’, the reset is due to core lockup.
Bit 6 OBFAIL:
When set to ‘1’, the reset is due to an Option byte load failure (may be set with other bits).
Bit 5 WKUP:
When set to ‘1’, the reset is due to a wake-up from deep sleep.
Bit 4 SWRST:
When set to ‘1’, the reset is due to a software reset.
Bit 3 WDG:
When set to ‘1’, the reset is due to watchdog expiration.
Bit 2 PIN:
When set to ‘1’, the reset is due to an external reset pin signal.
Bit 1 PWRLV:
When set to ‘1’, the reset is due to the application of a Core power supply (or previously
failed).
Bit 0 PWRHV:
Always set to ‘1’, Normal power applied.
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