STM32W108C8 Datasheet, PDF (48/275 Pages) –

System modules
STM32W108C8
6.2.3
Reset generation
The Reset Generation module responds to reset sources and generates the following reset
signals:
• PORESET
Reset of the ARM® Cortex-M3 CPU and ARM® Cortex-M3
System Debug components (Flash Patch and Breakpoint,
Data Watchpoint and Trace, Instrumentation Trace Macrocell,
Nested Vectored Interrupt Controller). ARM defines
PORESET as the region that is reset when power is applied.
• SYSRESET
Reset of the ARM® Cortex-M3 CPU without resetting the
Core Debug and System Debug components, so that a live
system can be reset without disturbing the debug
configuration.
• DAPRESET
Reset to the SWJ's AHB Access Port (AHB-AP).
• PRESETHV
Peripheral reset for always-on power domain, for peripherals
that are required to retain their configuration across a deep
sleep cycle.
• PRESETLV
Peripheral reset for core power domain, for peripherals that
are not required to retain their configuration across a deep
sleep cycle.
Table 5 shows which reset sources generate certain resets.
Reset source
POR HV
POR LV (in deep sleep)
POR LV (not in deep
sleep)
RSTB
Watchdog reset
Software reset
Option byte error
Normal deep sleep
Emulated deep sleep
Debug reset
Table 5. Generated resets
Reset generation
PORESET
X
X
SYSRESET DAPRESET PRESETHV PRESETLV
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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DocID018587 Rev 4