STM32W108C8 Datasheet, PDF (110/275 Pages) –

Serial interfaces
STM32W108C8
Parameter
Direction
GPIO
configuration
SC1 pin
SC2 pin
Table 20. SPI master GPIO usage
MOSI
MISO
SCLK
Output
Input
Output
Alternate Output
(push-pull)
PB1
Input
PB2
Alternate Output (push-pull)
Special SCLK mode
PB3
PA0
PA1
PA2
9.3.1
Setup and configuration
Both serial controllers, SC1 and SC2, support SPI master mode. SPI master mode is
enabled by the following register settings:
• The serial controller mode register (SCx_CR) is ‘2’.
• The MSTR bit in the SPI configuration register (SCx_SPICR) is ‘1’.
• The ACK bit in the I²C control register (SCx_I2CCR2) is ‘1’.
The SPI serial clock (SCLK) is produced by a programmable clock generator. The serial
clock is produced by dividing down 12 MHz according to this equation:
Rate = -₍--_L----_I--_N--¹----+²---^M-₁----₎-^H--_x--^z-₂---_E----_X---_P-
EXP is the value written to the SCx_CRR2 register and LIN is the value written to the
SCx_CRR1 register. The SPI master mode clock may not exceed 6 Mbps, so EXP and LIN
cannot both be zero.
The SPI master controller supports various frame formats depending upon the clock polarity
(CPOL), clock phase (CPHA), and direction of data (LSBFIRST) (see SPI master mode
formats on page 111). The bits CPOL, CPHA, and LSBFIRST are defined within the
SCx_SPICR register.
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