STM32W108C8 Datasheet, PDF (130/275 Pages) –

Serial interfaces
STM32W108C8
9.8.3
Serial controller interrupt control register 1 (SCx_ICR)
Address offset: 0xA854 (SC1_ICR) and 0xA858 (SC2_ICR)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
IDLE TXE RXNE
LEVEL LEVEL LEVEL
rw
rw
rw
Bits 31:3 Reserved, must be kept at reset value
Bit 2 IDLELEVEL: Trigger event configuration to generate the IDLE interrupt
This bit is set and cleared by software.
0: Idle interrupt is generated on edge
1: Idle interrupt is generated on level
Bit 1 TXELEVEL: Trigger event configuration to generate the TXE interrupt
This bit is set and cleared by software.
0: TXE interrupt is generated on edge
1: TXE interrupt is generated on level
Bit 0 RNXNELEVEL: Trigger event configuration to generate the RXNE interrupt
This bit is set and cleared by software.
0: RXNE interrupt is generated on edge
1: RXNE interrupt is generated on level
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DocID018587 Rev 4