STM32W108C8 Datasheet, PDF (131/275 Pages) –

STM32W108C8
Serial interfaces
9.8.4
Serial controller data register (SCx_DR)
Address offset: 0xC83C (SC1_DR) and 0xC03C (SC2_DR)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
Reserved
8
7
6
5
4
3
2
1
0
DR[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value
Bits 7:0 DR[7:0]: Transmit and receive data register
Writing to this register adds a byte to the transmit FIFO. Reading from this register takes the
next byte from the receive FIFO and clears the overrun error bit if it was set. In UART mode
(SC1 only), reading from this register loads the UART status register with the parity and
frame error status of the next byte in the FIFO, and clears these bits if the FIFO is empty.
9.8.5
Serial controller control register 2 (SCx_CR)
Address offset: 0xC854 (SC1_CR) and 0xC054 (SC2_CR)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
MODE[1:0]
rw
rw
Bits 31:2 Reserved, must be kept at reset value
Bits 1:0 MODE[1:0]: Serial controller mode selection
This bit-field specifies the serial control operating mode
00: No mode selected
01: UART mode
10: SPI mode
11: I2C mode
Note: If the UART mode is supported only by SC1
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