STE2007 Datasheet, PDF (40/62 Pages) STMicroelectronics – 96 x 68 Single Chip LCD Controller/Driver

7 Power ON/Power OFF timing Sequence
7 Power ON/Power OFF timing Sequence
STE2007
In Figure 33 is the timing diagram for power on/power down sequences.
Figure 33. Timing for phone’s power on sequence when VDD,VDDCP Up before VDDI
VDDI
VDD
Inputs
Outputs
!CS
!RES
INTERNAL
RESET
tp1 > 0
tp1 > 0
tpi >0µs
tpi >0µs
High-Z
tcs >0µs
tcs >0µs
tp2 >0µs
t_PWROFF1 >0 ms
t_PWROFF2 >20ms
Reset State
trs = max. 5µs
Trs = max. 5µs
High-Z
Reset State
XCS,SDAIN,XRES can become ”High” simultaneously with VDDI (tcs>0,tpi>0;tp2>0).
trs= max 5000ns (Internal Reset Time- see AC Characteristics Paragraph)
t_PWROFF1>0ms must be considered when driver is in Power Saver or Booster OFF status
t_PWROFF2>20ms must be considered when driver is in Normal Working Condition
VDDI, VDD and VDD_CP can come up/go down in any sequence
VDDI can be Up with VDD, VDDCP down and viceversa. If only one supply rail is up, the driver
is forced in reset state.
If VDD is high after VDDI all timing referred to VDDI must be referred to VDD (Fig. 24)
Figure 34. Timing for phone’s power on sequence when VDDI Up before VDD
VDDI
VDD
SDAIN
SDAOUT
!CS
!RES
INTERNAL
RESET
tp1 < 0
tp1 < 0
tpi >0µs
tpi >0µs
High-Z
tcs >0µs
tcs >0µs
tp2 >0µs
t_PWROFF1 >0 ms
t_PWROFF2 >20ms
trs = max. 5µs
Reset State
Trs = max. 5µs
High-Z
Reset State
40/62