STE2007 Datasheet, PDF (27/62 Pages) STMicroelectronics – 96 x 68 Single Chip LCD Controller/Driver

STE2007
5 Display Data RAM (DDRAM)
5 Display Data RAM (DDRAM)
5.1
DDRAM and Page/column address circuit
The DDRAM stores pixel data for LCD. It is a 68–row (8 page by 8 bits +4) by 96–column
addressable array. D7 to D0 display data from MCU corresponds to the LCD common direction.
”0” bit in DDRAM is a OFF–dot on display and ”1” bit in DDRAM is displayed as ON–dot on
display.
Figure 20. DDRAM vs. display on LCD
D0 0 1 1 1
1
D1 1 0 0 0
0
D2 0 0 0 0
1
D3 0 0 1 1
0
D4 1 1 0 0
1
±±
DDRAM
COM0
COM1
COM2
COM3
COM4
±±
Display on LCD
Each pixel can be selected when page address and column address are specified. The MCU
issues Page address set command to change the page and access to another page. In
DDRAM page address 8 (D3,D2,D1,D0=1,0,0,0) only display data D0,D1,D2 & D3 are valid.
The DDRAM column address is specified by Column address set command.
The specified column address is automatically incremented by +1 when a Display data write
command is entered. After the last column address (5Fh), column address returns to 00h and
page address incremented by +1. After the very last address (column=5Fh, page=8h), both
column address and page address return to 00h (column address=00h, page address=0h).
Figure 21. Column address in normal mode
Data
LSBit D0 Data for page address 0H to 07H
D1
D2
D3
D4
D5
0H
D6
1H
MSBit D7
2H
3H
Page address _4H
012
96 97 98
192 193 194
288 289 290
384 385 386
5H 480 481 482
6H 576 577 578
7H 672 673 674
8H 768 769 770
00H 01H 02H
D0
Column address
D1 _{Data for page address 8H}
D2
D3
94 95
190 191
286 287
382 383
478 479
574 575
670 671
766 767
862 863
5EH 5FH
27/62