STE2007 Datasheet, PDF (23/62 Pages) STMicroelectronics – 96 x 68 Single Chip LCD Controller/Driver

STE2007
Figure 15. Bit transfer and START,STOP conditions definition
CLOCK
DATA LINE
STABLE
DATA VALID
4 INTERFACE
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
D00IN1151
STOP
CONDITION
Figure 16. Acknowledgment on the I²C-bus
START
SCLK FROM
MASTER
1
2
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
MSB
D00IN1152
CLOCK PULSE FOR
ACKNOWLEDGEMENT
8
9
LSB
4.3.1
Communication Protocol
The STE2007 is an I²C slave. The access to the device is bi-directional since data write and
status read are allowed.
Four are the device addresses available for the device. All have in common the first 5 bits
(01111). The two least significant bit of the slave address are set by connecting the SA0 and
SA1 inputs to a logic 0 or to a logic 1.
4.3.2
Starting the Communication
To start the communication between the bus master and the slave LCD driver, the master must
initiate a START condition. Following this, the master sends an 8-bit byte, on the SDA bus line
(Most significant bit first). This consists of the 7-bit Device Address Code, and the 1-bit Read/
Write Designator (R/W). The R/W bit has to be set to logic 1 to logic 0 according to the type of
communication (read or write).
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the
I²C-bus transfer.
STE2007
SLAVE ADDRESS
ADDRESS BYTE
SSR
0 1 1 1 1AA /
1 0W
READ or WRITE
DESIGNATOR
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