STE2007 Datasheet, PDF (24/62 Pages) STMicroelectronics – 96 x 68 Single Chip LCD Controller/Driver

4 INTERFACE
STE2007
4.3.3
MCU TxData Mode (Write Mode)
If the R/W bit is set to logic 0 the STE2007 is set to be a receiver and the master can send
commands or data.
After the communication has started and slaves have acknowledged, the master sends a
control byte defined as follows and waits for its acknowledgement:
CONTROL BYTE
Co DC 0 0 0 0 0 0
The Co bit is the control byte MSB and defines if after this control byte will follow a single byte
sequence (Co = 1) or a multiple bytes sequence (Co = 0). The D/C bit defines whether the
following byte (if Co = 1) or the following stream of bytes (if Co = 0) are command (D/C = 0) or
DDRAM data (D/C = 1).
Depending on state of flags Co and D/C, four writing sequences are possible:
SINGLE COMMAND BYTE SEQUENCE (Co = 1, D/C = 0): a single byte interpreted as a
command will follow the control byte;
SINGLE DATA BYTE SEQUENCE (Co = 1, D/C = 1): a single byte interpreted as a data to be
written in DDRAM will follow the control byte;
MULTIPLE COMMAND BYTES SEQUENCE (Co = 0, D/C = 0): a stream of bytes will follow the
control byte, with each single byte interpreted as a command;
MULTIPLE DATA BYTES SEQUENCE (Co = 0, D/C = 1): a stream of bytes will follow the
control byte, with each byte interpreted as a data byte to be written in DDRAM.
Every single byte of a sequence must be acknowledged by all addressed units.
A multiple data sequence is terminated only by sending a STOP condition on the I²C bus.
When a sequence is terminated, another sequence of any type can follow or a I²C STOP
condition can be sent to close the communication.
In a single or multiple data bytes sequence, every data byte received is stored in the DDRAM at
the location specified by the current values of data pointers. Data pointers are automatically
updated after each single data byte written.
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