STD11N65M2 Datasheet, PDF (4/21 Pages) STMicroelectronics – Extremely low gate charge

Electrical characteristics
STD11N65M2, STP11N65M2, STU11N65M2
2
Electrical characteristics
(T_C = 25 °C unless otherwise specified)
Symbol
Parameter
Table 5. On /off states
Test conditions
Drain-source
V_{(BR)DSS breakdown voltage}
V_GS = 0, I_D = 1 mA
Zero gate voltage
I_DSS
drain current
I_GSS
Gate-body leakage
current
V_GS = 0, V_DS = 650 V
V_GS = 0, V_DS = 650 V,
T_C=125 °C
V_DS = 0, V_GS = ± 25 V
V_GS(th)
R_DS(on)
Gate threshold voltage V_DS = V_GS, I_D = 250 μA
Static drain-source
on-resistance
V_GS = 10 V, I_D = 3.5 A
Min. Typ. Max. Unit
650
V
1 μA
100 μA
±10 μA
2
3
4V
0.6 0.67 Ω
Symbol
Parameter
Table 6. Dynamic
Test conditions
Min. Typ. Max. Unit
C_iss
C_oss
C_rss
Input capacitance
Output capacitance
Reverse transfer
capacitance
V_GS = 0, V_DS = 100 V,
f = 1 MHz,
- 410 - pF
-
20
- pF
- 0.95 - pF
(1) ^{Equivalent output}
C_{oss eq. capacitance}
V_GS = 0, V_DS = 0 to 520 V
-
83
- pF
Intrinsic gate
R_{G resistance}
f = 1 MHz, I_D=0
-
6.4
-
Ω
Q_g Total gate charge
V_DD = 520 V, I_D = 7 A,
Q_gs Gate-source charge _{VGS = 10 V (see Figure 17)}
Q_gd Gate-drain charge
- 12.5 - nC
-
3.2
- nC
-
5.8
- nC
1. C_{oss eq.} is defined as a constant equivalent capacitance giving the same charging time as C_oss when V_DS
increases from 0 to 80% V_DSS
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