STM32F777XX Datasheet, PDF (32/255 Pages) STMicroelectronics – Dual mode Quad-SPI

Functional overview
STM32F777xx STM32F778Ax STM32F779xx
2.19.2
• LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
– LPR operates in normal mode (default mode when LPR is ON)
– LPR operates in under-drive mode (reduced leakage mode).
• Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
Two external ceramic capacitors should be connected on V_{CAP_1} and V_{CAP_2} pin.
All packages have the regulator ON feature.
Table 3. Voltage regulator configuration mode versus device operating mode⁽¹⁾
Voltage regulator
configuration
Run mode
Sleep mode
Stop mode
Standby mode
Normal mode
MR
MR
MR or LPR
-
Over-drive
mode⁽²⁾
MR
MR
-
-
Under-drive mode
-
-
MR or LPR
-
Power-down
mode
-
-
-
Yes
1. ‘-’ means that the corresponding configuration is not available.
2. The over-drive mode is not available when V_DD = 1.7 to 2.1 V.
Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V₁₂ voltage source through V_{CAP_1} and V_{CAP_2} pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency.The two 2.2 μF ceramic capacitors should
be replaced by two 100 nF decoupling capacitors.
When the regulator is OFF, there is no more internal monitoring on V₁₂. An external power
supply supervisor should be used to monitor the V₁₂ of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V₁₂ power domain.
In the regulator OFF mode, the following features are no more supported:
• PA0 cannot be used as a GPIO pin since it allows to reset a part of the V₁₂ logic power
domain which is not reset by the NRST pin.
• As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
• The over-drive and under-drive modes are not available.
• The Standby mode is not available.
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DocID028294 Rev 4