S71WS512N Datasheet, PDF (15/18 Pages) SPANSION – Migrating from the S71WS512N to the S71WS512P

Application Note
Table 6.6 S29WS512P Erase / Programming Performance
Parameter
JEDEC Standard
Description
t_AVAV
t_WC Write Cycle Time
Synchronous (Legacy
Mode)
t_AVWL
t_AS
Address Setup Time
Asynchronous (Legacy
Mode)
Synchronous (Zero Hold
Mode)
Asynchronous (Zero Hold
Mode)
Synchronous (Legacy
Mode)
t_WLAX
t_AH
Address Hold Time
Asynchronous (Legacy
Mode)
Synchronous (Zero Hold
Mode)
Asynchronous (Zero Hold
Mode)
t_DVWH
t_WHDX
t_GHWL
t_WHEH
t_WLWH
t_WHWL
t_ELWL
t_AVDP
t_DS
t_DH
t_GHWL
t_CAS
t_CH
t_WP
t_WPH
t_SR/W
t_VID
t_VIDS
t_CS
t_AVSW
t_AVHW
t_AVSC
AVD# Low Time
Data Setup Time
Data Hold Time
Read Recovery Time Before Write
CE# Setup Time to AVD#
CE# Hold Time
Write Pulse Width
Write Pulse Width High
Latency Between Read and Write Operations
V_ACC Rise and Fall Time
V_ACC Setup Time (During Accelerated Programming)
CE# Setup Time to WE#
AVD# Setup Time to WE#
AVD# Hold Time to WE#
AVD# Setup Time to CLK
Legacy Mode
Zero Hold Mode
t_AVHC AVD# Hold Time to CLK
Legacy Mode
Zero Hold Mode
t_SEA
t_ESL
t_PSL
t_ASP
t_PSP
t_CSW
t_WEP
Sector Erase Accept Time-out
Erase Suspend Latency
Program Suspend Latency
Toggle Time During Erase within a Protected Sector
Toggle Time During Programming Within a Protected Sector
Clock Setup Time to WE#
Noise Pulse Margin on WE#
54
MHz
Min
66
80
MHz MHz
60
108
MHz Unit
ns
5
5
5
3.5
2
2
2
2
Min
ns
9
9
9
6
6
6
6
6
7
7
6
5
7
7
6
5
Min
ns
0
0
0
0
0
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
5
Min
6
5
Min
0
Min
Min
Min
Typ
Typ
—
Max
0
0
6
20
0
0
0
0
25
20
0
500
1
4
4
4
5
5
6
6
5
5
0
0
50
20
20
0
0
—
3
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
3
ns
6
3
ns
0
µs
µs
µs
µs
µs
—
ns
October 3, 2006 2xWS-N_to_WS-P_AN_01E
S71WS512N to S71WS512P
15