S71WS512N Datasheet, PDF (13/18 Pages) SPANSION – Migrating from the S71WS512N to the S71WS512P

Application Note
Table 6.4 S29WS512P Synchronous Burst Read
Parameter
t_IACC
t_BACC
t_ACS
t_ACH
t_BDH
t_RDY = t_CR
t_OE
t_CEZ
t_OEZ
t_CES
t_RACC
t_CAS
t_AVC
t_AVD
Description
Synchronous Access Time
Burst Access Time Valid Clock to Output Delay
Address Setup Time to Clock
Address Hold Time from Clock
Data Hold Time
Chip Enable to RDY Active
Output Enable to RDY Low
Chip Enable to High Z
Output Enable to High Z
CE# Setup Time to Clock
Ready Access Time from Clock
CE# Setup Time to AVD#
AVD# Low to Clock Setup Time
AVD# Pulse
Mode
Legacy
Zero Hold
Legacy
Zero Hold
Legacy
Zero Hold
54 MHz 66 MHz 80 MHz 108 MHz Unit
Max
80
ns
83
Max 13.5
11.2
9
7
ns
5
4
4
3.5
Min
ns
6
6
6
6
6
6
5
Min
0
0
0
5
ns
0
Min
4
3
3
2
ns
Max
7
ns
Max 13.5
11.2
9
7
ns
Max
10
10
10
7
ns
Max
10
10
10
7
ns
Min
4
4
4
3.5
ns
Max 13.5
11.2
9
6
ns
Min
0
0
0
0
ns
Min
4
4
4
5
ns
Min
8
8
8
6
ns
October 3, 2006 2xWS-N_to_WS-P_AN_01E
S71WS512N to S71WS512P
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