S71WS512N Datasheet, PDF (12/18 Pages) SPANSION – Migrating from the S71WS512N to the S71WS512P

Application Note
Table 6.2 S29WS512P Asynchronous Read
Parameter
Description
t_CE
t_ACC
Access Time from CE# Low
Asynchronous Access Time
t_AVDP
t_AAVDS
AVD# Low Time
Address Setup Time to Rising Edge of AVD#
t_AAVDH
Address Hold Time from Rising Edge of AVD#
t_OE
t_OEH
t_OEZ
t_CAS
t_PACC
Output Enable to Output Valid
Output Enable Hold
Time
Read
Toggled and Data#
Polling
Output Enable to High Z
CE# Setup Time to AVD#
Intra Page Access Time
Mode
54 MHz 66 MHz 80 MHz 108 MHz Unit
Zero Hold
83
Max
ns
Legacy
80
Zero Hold
83
Max
ns
Legacy
80
—
Min
8
8
8
7.5
ns
Zero Hold Min
4
4
4
3.5
ns
Legacy Min
8
8
8
7.5
ns
Zero Hold Min
7
6
6
4
ns
Legacy Min
0
0
0
0
ns
Max
6
ns
Min
0
0
0
0
ns
Min
10
10
10
6
ns
Max 10
10
10
Min
0
0
0
Max 20
20
20
7
ns
0
ns
20
ns
Table 6.3 S29WS256N Synchronous Burst Read
Parameter
t_IACC
t_BACC
t_ACS
t_ACH
t_BDH
t_RDY = t_CR
t_OE
t_CEZ
t_OEZ
t_CES
t_RACC
t_CAS
t_AVC
t_AVD
Description
Synchronous Access Time
Burst Access Time Valid Clock to Output Delay
Address Setup Time to Clock
Address Hold Time from Clock
Data Hold Time
Chip Enable to RDY Active
Output Enable to RDY Low
Chip Enable to High Z
Output Enable to High Z
CE# Setup Time to Clock
Ready Access Time from Clock
CE# Setup Time to AVD#
AVD# Low to Clock Setup Time
AVD# Pulse
Mode
54 MHz 66 MHz 80 MHz 108 MHz Unit
Max
80
—
ns
Max 13.5
11.2
9
—
ns
Min
5
4
—
ns
Min
7
6
—
ns
Min
4
3
—
ns
Max 13.5
11.2
9
—
ns
Max 13.5
11.2
—
ns
Max
10
—
ns
Max
10
—
ns
Min
4
—
ns
Max 13.5
11.2
9
—
ns
Min
0
—
ns
Min
4
—
ns
Min
8
—
ns
12
S71WS512N to S71WS512P
2xWS-N_to_WS-P_AN_01E October 3, 2006