S71WS512N Datasheet, PDF (14/18 Pages) SPANSION – Migrating from the S71WS512N to the S71WS512P

Application Note
Table 6.5 S29WS256N Erase / Programming Performance
Parameter
JEDEC Standard
Description
t_AVAV
t_AVWL
t_WC
Write Cycle Time
t_AS
Address Setup Time
Synchronous
Asynchronous
t_WLAX
t_AH
Address Hold Time
Synchronous
Asynchronous
t_DVWH
t_WHDX
t_GHWL
t_WHEH
t_WLWH
t_WHWL
t_ELWL
t_AVDP
t_DS
t_DH
t_GHWL
t_CAS
t_CH
t_WP
t_WPH
t_SR/W
t_VID
t_VIDS
t_CS
t_AVSW
t_AVHW
t_AVSC
t_AVHC
t_SEA
t_ESL
t_PSL
t_ASP
t_PSP
AVD# Low Time
Data Setup Time
Data Hold Time
Read Recovery Time Before Write
CE# Setup Time to AVD#
CE# Hold Time
Write Pulse Width
Write Pulse Width High
Latency Between Read and Write Operations
V_ACC Rise and Fall Time
V_ACC Setup Time (During Accelerated Programming)
CE# Setup Time to WE#
AVD# Setup Time to WE#
AVD# Hold Time to WE#
AVD# Setup Time to CLK
AVD# Hold Time to CLK
Sector Erase Accept Time-out
Erase Suspend Latency
Program Suspend Latency
Toggle Time During Erase within a Protected Sector
Toggle Time During Programming Within a Protected
Sector
t_CSW
t_WEP
Clock Setup Time to WE#
Noise Pulse Margin on WE#
54 MHz 66 MHz 80 MHz 108 MHz Unit
Min
80
—
ns
5
Min
0
—
ns
—
ns
9
Min
20
—
ns
—
Min
8
—
ns
Min 45
20
—
ns
Min
0
—
ns
Min
0
—
ns
Min
0
—
ns
Min
0
—
ns
Min
30
—
ns
Min
20
—
ns
Min
0
—
ns
Min
500
—
ns
Min
1
—
µs
Min
5
—
ns
Min
5
—
ns
Min
5
—
ns
Min
5
—
ns
Min
5
—
ns
Max
50
—
µs
Max
20
—
µs
Max
20
—
µs
Typ
0
—
µs
Typ
0
—
µs
Min
5
Max
3
—
ns
—
ns
14
S71WS512N to S71WS512P
2xWS-N_to_WS-P_AN_01E October 3, 2006