LAN9218 Datasheet, PDF (85/130 Pages) SMSC Corporation – High-Performance Single- Chip 10/100 Ethernet Controller with HP Auto-MDIX

High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
5.3.16 GPT_CNT-General Purpose Timer Current Count Register
Offset:
90h
Size:
This register reflects the current value of the GP Timer.
32 bits
BITS
DESCRIPTION
31-16 Reserved
15-0 General Purpose Timer Current Count (GPT_CNT). This 16-bit field
reflects the current value of the GP Timer.
TYPE
RO
RO
DEFAULT
-
FFFFh
5.3.17 WORD SWAP—Word Swap Control
Offset:
98h
Size:
32 bits
This register controls how words from the host data bus are mapped to the CSRs and Data FIFOs
inside the LAN9218. The LAN9218 always sends data from the Transmit Data FIFO to the network so
that the low order word is sent first, and always receives data from the network to the Receive Data
FIFO so that the low order word is received first.
BITS
31:0
DESCRIPTION
Word Swap. This field only has significance if the device is operated in 16-
bit mode. In 32-bit mode, D[31:15] is always mapped to the high order word
and D[15:0] is always mapped to the low order word. In 16-bit mode, if this
field is set to 00000000h, or anything except 0xFFFFFFFFh, the LAN9218
maps words with address bit A[1]=1 to the high order words of the CSRs
and Data FIFOs, and words with address bit A[1]=0 to the low order words
of the CSRs and Data FIFOs. If this field is set to 0xFFFFFFFFh, the
LAN9218 maps words with address bit A[1]=1 to the low order words of the
CSRs and Data FIFOs, and words with address bit A[1]=0 to the high order
words of the CSRs and Data FIFOs.
Note: Please refer to Section 3.6.1, "32-bit vs. 16-bit Host Bus Width
Operation" for additional information.
TYPE
R/W
NASR
DEFAULT
00000000h
SMSC LAN9218
85
DATASHEET
Revision 1.5 (07-18-06)