LAN9218 Datasheet, PDF(119/130 Page) SMSC Corporation – High-Performance Single- Chip 10/100 Ethernet Controller with HP Auto-MDIX

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LAN9218 Datasheet, PDF (119/130 Pages) SMSC Corporation – High-Performance Single- Chip 10/100 Ethernet Controller with HP Auto-MDIX

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High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

Datasheet

Note: An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The

cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de-

asserted in any order.

6.5

RX Data FIFO Direct PIO Burst Reads

In this mode the upper address inputs are not decoded, and any burst read of the LAN9218 will read

the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This

is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode

is useful when the host processor must increment its address when accessing the LAN9218. Timing

is identical to a PIO Burst Read, and the FIFO_SEL signal has the same timing characteristics as the

address lines.

In this mode, performance is improved by allowing an unlimited number of back-to-back DWORD or

WORD read cycles. RX Data FIFO Direct PIO Burst Reads can be performed using Chip Select (nCS)

or Read Enable (nRD). When either or both of these control signals go high, they must remain high

for the period specified.

Timing for 16-bit and 32-bit RX Data FIFO Direct PIO Burst Reads is identical with the exception that

D[31:16] are not driven during a 16-bit burst. Note that address lines A[2:1] are still used, and address

bits A[7:3] are ignored.

FIFO_SEL

A[2:1]

nCS, nRD

Data Bus

Figure 6.4 RX Data FIFO Direct PIO Burst Read Cycle Timing

Note: The âData Busâ width is 32 bits with optional support for 16-bit bus widths.

Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing

SYMBOL DESCRIPTION

tcsh

nCS, nRD Deassertion Time

tcsdv

nCS, nRD Valid to Data Valid

tacyc

Address Cycle Time

tasu

Address, FIFO_SEL Setup to nCS, nRD Valid

tadv

Address Stable to Data Valid

tah

Address, FIFO_SEL Hold Time

tdon

Data Buffer Turn On Time

SMSC LAN9218

119

DATASHEET

MIN

TYP

MAX UNITS

Revision 1.5 (07-18-06)

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