LAN9218 Datasheet, PDF (120/130 Pages) SMSC Corporation – High-Performance Single- Chip 10/100 Ethernet Controller with HP Auto-MDIX

High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing
SYMBOL
t_doff
t_doh
DESCRIPTION
Data Buffer Turn Off Time
Data Output Hold Time
MIN
TYP
MAX UNITS
7
ns
0
ns
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
6.6
PIO Writes
PIO writes are used for all LAN9218 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). Either or both of these control signals must go high between cycles for the
period specified.
PIO Writes are valid for 16- and 32-bit access. Timing for 16-bit and 32-bit PIO write cycles are
identical with the exception that D[31:16] are ignored during a 16-bit write.
A[7:1]
nCS, nRD
Data Bus
Figure 6.5 PIO Write Cycle Timing
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths.
Table 6.7 PIO Write Cycle Timing
SYMBOL DESCRIPTION
MIN
t_cycle
Write Cycle Time
45
t_csl
nCS, nWR Assertion Time
32
t_csh
nCS, nWR Deassertion Time
13
t_asu
Address Setup to nCS, nWR Assertion
0
t_ah
Address Hold Time
0
t_dsu
Data Setup to nCS, nWR Deassertion
7
Revision 1.5 (07-18-06)
120
DATASHEET
TYP
MAX UNITS
ns
ns
ns
ns
ns
ns
SMSC LAN9218