LAN83C180_01 Datasheet, PDF (8/22 Pages) SMSC Corporation – 10/100 Fast Ethernet PHY Transceiver

RX10 Latency
When connected to appropriate magnetics the latency through the RX10 path is less than 6BT (600ns). This timing
is measured from the input of the receive magnetics to the falling edge of RX_CLK. The RX10 path may ignore up to
three Manchester encoded bits at the start of data reception (802.3 allows up to 5 bits).
100BASE-TX OPERATION
100Mb/s Data Exchange on the MII Interface
100Mb/s data is transferred across the MII with clock speeds of 25MHz. The MAC outputs data to the LAN83C180
via the MII interface, on the TXD[3:0] bus. This data is synchronized to the rising edge of TX_CLK. To indicate that
there is valid data for transmission on the MII, the MAC sets the TX_EN signal active. This forces the LAN83C180
device to take in the data on the TXD[3:0] bus and replace the first octet of the MAC preamble with Start-of-Stream
Delimiter (SSD) symbols to indicate the start of the Physical Layer Stream.
When the data transfer across the MII is complete, the MAC deasserts the TX_EN signal and the LAN83C180 adds
End-of-Stream Delimiters (ESD) symbols onto the end of the data stream. The complete data stream (the Physical
Layer Stream) is encoded from 4 bits into 5 bits, scrambled, converted to MLT3 and driven to the TXOP and TXON
pin differentially.
The TX100 path is disabled when not in 100BASE-TX mode and, with the exception of the RX100 Signal Detect, the
RX100 Receive Path is disabled when not in 100BASE-TX mode.
125MHz Synthesizer
This synthesizer employs a phase-locked loop (PLL) to generate a 125MHz timing reference from the 25MHz
reference clock. This 125MHz reference is used by the 100BASE-TX transmit function and is divided by 5 to provide
a 25MHz data strobe on TX_CLK. TX_CLK is frequency and phase locked to the 25MHz reference with a small
phase offset. The synthesizer is disabled when not in 100BASE-TX mode.
TX100 PISO, Encoder and Scrambler
The TX100 PISO, Encoder and scrambler loads data from the MII on the rising edge of TX_CLK, and converts them
to serial MLT3 for outputting to the TX100 Driver. The TXD[3] bit is output first. The PISO & Encoder do not operate
until the 125MHz Synthesizer is locked to the 25MHz reference. This avoids transmission of spurious signals onto
the twisted-pair.
TX100 Driver
The TX100 Driver outputs the differential signal onto the TXOP and TXON pins. It operates with 1:1 magnetics to
provide impedance matching and amplification of the signal in accordance with the 802.3 specifications. The
transmit current is governed by the current through the TXREF100 pin, which must be grounded through a resistor
as described in “External Components”. The TX100 driver is disabled in 10BASE-T mode and in loop back mode. If
no data is being transmitted from the MAC, the LAN83C180 outputs idle symbols of 11111 (suitably scrambled).
TX100 Latency
The transmit latency from the first TX_CLK rising when TX_EN is high to the first bit of the “J” symbol on the cable is
8BT.
RX100 Equalizer & Base-line Wander Correction
The RX100 Equalizer compensates for the signal attenuation and distortion resulting from transmission down the
cable and through the isolation transformers. The Equalizer is self-adjusting and is designed to restore signals
received from up to 10dB cable attenuation (at 16MHz). When the Equalizer is active it adjusts to the incoming
signal within 1ms. Thereafter, the Equalizer will continuously adjust to small variations in signal level without
corrupting the received data.
The 100BASE-TX MLT3 code contains significant low frequency components which are not passed through the
isolation transformers and cannot be restored by an adaptive equalizer. This leads to a phenomenon known as
base-line wander which will cause an unacceptable increase in error rate, if not corrected. The LAN83C180 employs
a quantized feedback technique to restore the low frequency components and thus maintain a very low error rate
even when receiving signals such as the “killer packet” described in the TP_PMD spec.
RX100 Clock Recovery
The RX100 Clock Recovery circuit uses a Phase-Locked Loop (PLL) to derive a sampling clock from the incoming
signal. The recovered clock runs at the symbol bit rate (nominally 125MHz) and is used to clock the MLT3 decoder
and the Serial to Parallel converter (SIPO). The recovered clock is divided by 5 to generate the receive clock
(RX_CLK) which is used to strobe received data across the MII interface. When no signal is detected in 100BASE-
TX mode, the PLL is locked to the reference clock and runs at 125MHz. This ensures that RX_CLK runs
continuously at 25MHz in 100BASE-TX mode. When a signal is present, the Clock Recovery PLL remains locked to
SMSC DS – LAN83C180
Page 8
Rev. 08/24/2001