LAN83C180_01 Datasheet, PDF (10/22 Pages) SMSC Corporation – 10/100 Fast Ethernet PHY Transceiver

CONTROLS
Initialization, mode selection and other options are governed by the control inputs and register as described in the
following paragraphs.
Initialization (nRESET)
The LAN83C180 incorporates a power-on-reset circuit for self-initialization on power-up. During initialization the
open-drain nRESET pin is driven low and all data outputs are disabled to prevent spurious outputs to the twisted-pair
and to the MII interface. nRESET will remain low until either the 10BASE-T or 100BASE-TX transceiver has been
correctly initialized. The LAN83C180 will then release nRESET allowing the external pull-up to pull the pin high. Data
transmission and reception will not commence until nRESET is high. This allows the user to extend the inactive
period by externally holding nRESET low. It will not normally be necessary for the user to reset the LAN83C180
because it is designed to automatically recover from fault conditions.
However, if required, the user may initialize the device by doing a hardware or software reset.
Reset Mode
There are two types of reset in the LAN83C180 - hardware and software. The hardware reset is activated by setting
the nRESET pin to logic 0, and holding it low for at least 100ns. This mode causes an over-all reset in the
LAN83C180 - both analog and digital circuitry are reset. While nRESET is low, the SPDST and FDST pins are
inputs, and are used to determine the speed and duplex capability which will be advertised during auto-negotiate. A
low on SPDST advertises 100M capability. A high on FDST advertises full duplex capability. The software reset is
activated by setting bit 15 in register 0 high. This bit is a self clear bit and causes a partial reset of the device.
Following is a table summarizing the different blocks to be reset and which reset will affect them:
BLOCK
Management Register
PCS state machine (RCV, XMT, ANEG)
XMT Scrambler
RCV Scramble
LAN83C180 Control State Machine
LAN83C180 Analog
HW RESET
Yes
Yes
Yes
Yes
Yes
Yes
SW RESET
Yes
Yes
Yes
Yes
No
No
During both hardware and software resets, the ACTST, COLST and LNKST LED's will turn on for the duration of the
reset and stay on for at least 1 mS after the reset event has ended.
Holding nRESET low will not hold the device in a static, low power state. It will initialize the selected transceiver and
start the appropriate clocks. If the reset event is at power up, the clocks are stable 1.4msec max (typ.: 800usec)
following the nRESET signal assertion and Vcc ramped to a stable 5V. In case of the nRESET assertion at other
times, clocks are stable only a few (typ.: ~1usec) microseconds after the nRESET assertion.
Note: For power saving, use the low-power mode.
Low-Power Mode
This function is set via the management interface. Using MDC/MDIO, Bit 11 of register 0 is written high to put the
LAN83C180 into Low-Power mode. In this mode the 10BASE-T and 100BASE-TX transceivers are disabled. This
mode is intended to conserve power when the network connection is not required and the TXOP/TXON output is
undriven. The oscillator continues to run. Both RX_CLK and TX_CLK are stopped, the RXD bus is held low and TXD,
TXEN, and TXER are ignored. MDC and MDIO are still active for new commands.
Loopback Mode
Diagnostic loopback may be selected at any time by asserting setting Bit 14 in register 0. In 10BASE-T mode
transmission to the TXOP/ TXON output will be stopped and the RX10 Clock Recovery will receive input from the
TX10 transmit path rather than from the RXIP/RXIN inputs. In 100BASE-TX mode transmission to the TXOP/TXON
output will be stopped and the RX100 Clock Recovery will receive input from the TX100 transmit path.
Repeater Mode
Setting the RPTR pin high puts the LAN83C180 into repeater mode. In this mode the CRS will be active on receive
only. In 100Mbps RPTR mode, the LAN83C180 is able to perform a disconnect function from the MII. This function
is enabled by bit 24 in register 0. The default of this bit is 1 (enable) for repeater mode. (Note: if RPTR is low, this bit
has no effect). The LAN83C180 will disconnect from the MII if it receives two consecutive false CRS events with no
good frame in between them or if a false CRS event is longer then 480 +/- 4 bit time. If the LAN83C180 receives a
good carrier event (480 +/- 4 bit time) or a good idle event (idle symbols for a period of 25000 to 30000 bit time) it will
resume frame transfer to the MII.
SMSC DS – LAN83C180
Page 10
Rev. 08/24/2001