LAN83C180_01 Datasheet, PDF (16/22 Pages) SMSC Corporation – 10/100 Fast Ethernet PHY Transceiver

Reg 24 - LAN83C180 Specific Register
BIT
15:14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BIT NAME
Test Access
LED Control
MINT POL
Pol Dis
SQE Disable
JAB Disable
Loop 10
Force RX
Force TX
CRS_CTL
MF
Byp ALIGN
Byp ENC
Byp SCR
DISCEN
DESCRIPTION
Reserved SMSC test access only
0 = COLST active on collision
1 = COLST active on Sync/polarity
0 = MINT output active low
1 = MINT output active high
Disable 10BASE-T autopolarity correction
0 = SQE generation (normal operation)
1 = No SQE generation
0 = In case of jabber the 10BASE-T will cut the
frame (normal operation)
1 = Jabber function disable
Disable loopback of TX to RX in 10BASE-T half
duplex
Force reception regardless of link
Force transmission regardless of link
CRS behavior in FDX –
0 = CRS is active during transmission only
1= CRS active during reception only
0 = Normal operation
1 = Disable the MD preamble function
0 = Normal operation
1 = Bypass the aligner function
0 = Normal operation
1 = Bypass the 4B5B encoder function
0 = Normal operation
1 = Bypass the 4B5B scrambler function
Disconnect mechanism enable
Reg 25 - ANEG Status
BIT
BIT NAME
DESCRIPTION
15
Reserved
Test mode only - do not set high
14
Reserved
Test mode only - do not set high
13
Pol
10BASE-T polarity sense
12:8
PA
PHY address
7
Aneg complete 0 = Aneg completed
1 = Aneg did not complete (same as 1.5)
6
Duplex
ANEG result - duplex operation
0 = HDX, 1 = FDX
5
Speed
ANEG result - speed of operation
0 = 10, 1 = 100
4
Ability mtc 1 = abilities matched
0:3
ANEG state ANEG state machine current state
Reg 26 - Symbol Error Counter
BIT
BIT NAME
DESCRIPTION
15:0
RX_ERR
Number of RX_ERR events since last read –
counter
clears either in change of speed or read of this
reg.
DEFAULT TYPE
00b
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0 – DTE
1 – RPT
DEFAULT
0
0
0
PA<4:0>
0
TYPE
R/W
R/W
RO
RO
RO
0
RO
0
RO
0
RO
0
RO
DEFAULT TYPE
0
RO
SC
SMSC DS – LAN83C180
Page 16
Rev. 08/24/2001