LAN83C180_01 Datasheet, PDF (13/22 Pages) SMSC Corporation – 10/100 Fast Ethernet PHY Transceiver

MANAGEMENT
MAC Access to PHY Management Registers
The interface to these registers is via the MDC and MDIO signals. The address of the LAN83C180 is
specified by the PA<4:0> static inputs. The MD command is issued by the MAC and can be read or write:
COMMAND PREAMBLE
READ
32 Bits of 1
WRITE
32 Bits of 1
START
DATA
01b
01b
OP
CODE
10b
PHY
ADDRESS
5 Bits
REG
NUMBER
5 Bits
01b
5 Bits
5 Bits
TA
DATA
Z0b 16 bit from
PHY
10b 16 bit from
MAC
RESISTER SET
The following register set is implemented in the LAN83C180 device. Each of the registers is accessible to the MAC
at the specified offset. The bit types in the bit description tables follow the following convention:
SC = Self clear
RO = Read only
RW = Read or write
LL = Latch low until register read
LH = Latch high until register read
Res = Reserved
Reg 0 - Control Register
BIT
BIT NAME
DESCRIPTION
15
Reset
1 = PHY reset
0 = Normal operation
14
Loopback
1 = Loopback mode active
0 = Normal operation
13
Speed Selection 1 = 100 Mbps
0 = 10 Mbps
12
ANEG Enable
1 = Enable ANEG process
0 = Disable ANEG process
11
Power Down
1 = Power down active
0 = Normal operation
10
Isolation
1 = Isolation in process
0 = Normal operation
9
Restart ANEG
1 = Restart the ANEG process
0 = Normal operation
8
Duplex Selection 1= Full Duplex mode
0 = Half duplex mode
7
Collision Test
1 = Collision test active
0 = Normal operation
6:0
Reserved
Write as 0; ignore on read
DEFAULT
0
0
1
1
0
0
0
1
0
TYPE
RW
SC
RW
RW
RW
RW
RW
RW
SC
RW
RW
SMSC DS – LAN83C180
Page 13
Rev. 08/24/2001