COM20020I_06 Datasheet, PDF (59/65 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
t1
nRESET
nINTR
t2
Parameter
min typ
t1
nRESET Pulse Width***
t2
nINTR High to Next nINTR Low EF = 0
EF = 1
5TXTL^*
TDR**/2
4TXTL*
Note*: TXTL is period of external XTAL oscillation frequency.
Note**: TDR is period of Data Rate (i.e. at 2.5 Mbps, TDR = 400 nS)
Note***: When the power is turned on, t1 is measured from stable XTAL
oscillation after VDD was over 4.5V.
max units
FIGURE 23 – TTL INPUT TIMING ON XTAL1 PIN
t1
nRESET
nINTR
t2
Parameter
min typ
t1
nRESET Pulse Width***
t2
nINTR High to Next nINTR Low EF = 0
EF = 1
5TXTL^*
TDR**/2
4TXTL*
Note*: TXTL is period of external XTAL oscillation frequency.
Note**: TDR is period of Data Rate (i.e. at 2.5 Mbps, TDR = 400 nS)
Note***: When the power is turned on, t1 is measured from stable XTAL
oscillation after VDD was over 4.5V.
max units
FIGURE 24 – RESET AND INTERRUPT TIMING
SMSC COM20020I 3.3V
Page 59
DATASHEET
Revision 12-06-06