COM20020I_06 Datasheet, PDF (58/65 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
nTXEN
t4
nPULSE1
nPULSE2
t2
t1
t3
t1
t5
LAST BIT
(400 nS BIT TIME)
t2
t6
t8
RXIN
t7
Parameter
t1 nPULSE1, nPULSE2 Pulse Width
t2 nPULSE1, nPULSE2 Period
t3 nPULSE1, nPULSE2 Overlap
t4
nTXEN Low to nPULSE1 Low
t5
Beginning of Last Bit Time to nTXEN High
t6 RXIN Active Pulse Width
t7
RXIN Period
t8
RXIN Inactive Pulse Width
Note: Use Only 2.5 Mbps
min
typ
100
400
-10
0
850
250
10 100
400
20
max
+10
950
350
units
nS
nS
nS
nS
nS
nS
nS
nS
FIGURE 21 – NORMAL MODE TRANSMIT OR RECEIVE TIMING
(These signals are to and from the hybrid)
XTAL1
4.0V
t1
t2
1.0V
t3
50% of VDD
Parameter
t1
Input Clock High Time
t2
Input Clock Low Time
t3
Input Clock Period
t4
Input Clock Frequency
t5
Frequency Accuracy*
min typ max units
10
nS
10
nS
25
100 ^nS
10
40 MHz
-200
200 ppm
Note*: Input clock frequency must be 20 MHz (+- 100ppm or better) to use the internal Clock Multiplier.
t5 is applied to crystal oscillaton.
FIGURE 22 – BACKPLANE MODE TRANSMIT OR RECEIVE TIMING
(These signals are to and from the differential driver or the cable)
Revision 12-06-06
58
DATASHEET
SMSC COM20020I 3.3V