COM20020I_06 Datasheet, PDF (50/65 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
AD0-AD2,
D3-D7
nCS
ALE
nDS
DIR
VALID
t1
t2,
t4
t3
t11
t5
t9
VALID DATA
t12
t6
t13
t7
Note 2
t8**
t14
t8
t10
Parameter
min
max units
t1 Address Setup to ALE Low
t2 Address Hold from ALE Low
t3 nCS Setup to ALE Low
t4 nCS Hold from ALE Low
t5 ALE Low to nDS Low
t6 Valid Data Setup to nDS High
t7 Data Hold from nDS High
t8 Cycle Time (nDS to Next )**
t9 DIR Setup to nDS Active
t10 DIR Hold from nDS Inactive
t11 ALE High Width
t12 ALE Low Width
t13 nDS Low Width
t14 nDS High Width
20
nS
10
nS
10
nS
10
nS
15
nS
30
nS
10
nS
4TARB*
nS
10
nS
10
nS
20
nS
20
nS
20
nS
20
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 1: The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
** Note 2:
Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4TARB from the trailing edge of nDS to the leading edge of the
next nDS.
Write cycle for Address Pointer Low Register occurring after an access to
Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
FIGURE 13 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE
Revision 12-06-06
50
DATASHEET
SMSC COM20020I 3.3V