COM20020I_06 Datasheet, PDF (32/65 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
BIT
BIT NAME
6 Command
Chaining Enable
5 Transmit Enable
4,3 Extended
Timeout 1,2
2 Backplane
1,0 Sub Address 1,0
SYMBOL
CCHEN
TXEN
ET1, ET2
DESCRIPTION
This bit, if high, enables the Command Chaining operation of
the device. Please refer to the Command Chaining section
for further details. A low level on this bit ensures software
compatibility with previous SMSC ARCNET devices.
When low, this bit disables transmissions by keeping
nPULSE1, nPULSE2 if in non-Backplane Mode, and nTXEN
pin inactive. When high, it enables the above signals to be
activated during transmissions. This bit defaults low upon
reset. This bit is typically enabled once the Node ID is
determined, and never disabled during normal operation.
Please refer to the Improved Diagnostics section for details
on evaluating network activity.
These bits allow the network to operate over longer distances
than the default maximum 2 miles by controlling the
Response, Idle, and Reconfiguration Times. All nodes should
be configured with the same timeout values for proper
network operation. For the COM20020I with a 20 MHz
crystal oscillator, the bit combinations follow:
BACK-
PLANE
SUBAD
1,0
Reconfig
Response Idle Time Time
ET2
ET1 _{Time (μS) (μS)}
(mS)
0
0
596.6
656
840
0
1
298.4
328
840
1
0
149.2
164
840
1
1
37.4
41
420
Note: These values are for 5Mbps and RCNTMR[1,0]=00.
Reconfiguration time is changed by the RCNTMR1 and
RCNTMR0 bits.
A logic "1" on this bit puts the device into Backplane Mode
signaling which is used for Open Drain and Differential Driver
interfaces.
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD1
0
0
1
1
SUBAD0 Register
0 Tentative ID
1 Node ID
0 Setup 1
1 Next ID
See also the Sub Address Register.
Revision 12-06-06
32
DATASHEET
SMSC COM20020I 3.3V