COM20020I_06 Datasheet, PDF (33/65 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
BIT
7
6
5
4
3,2,1
0
BIT NAME
Pulse1 Mode
Four NACKS
Reserved
Receive All
Clock Prescaler Bits
3,2,1
Slow Arbitration
Select
Table 11 - Setup 1 Register
SYMBOL
DESCRIPTION
P1MODE
This bit determines the type of PULSE1 output driver used
in Backplane Mode. When high, a push/pull output is used.
When low, an open drain output is used. The default is
open drain.
FOUR
NACKS
This bit, when set, will cause the EXNACK bit in the
Diagnostic Status Register to set after four NACKs to Free
Buffer Enquiry are detected by the COM20020I. This bit,
when reset, will set the EXNACK bit after 128 NACKs to
Free Buffer Enquiry. The default is 128.
Do not set.
RCVALL
This bit, when set, allows the COM20020I to receive all
valid data packets on the network, regardless of their
destination ID. This mode can be used to implement a
network monitor with the transmitter on- or off-line. Note
that ACKs are only sent for packets received with a
destination ID equal to the COM20020I's programmed node
ID. This feature can be used to put the COM20020I in a
'listen-only' mode, where the transmitter is disabled and the
COM20020I is not passing tokens. Defaults low.
CKP3,2,1
These bits are used to determine the data rate of the
COM20020I. The following table is for a 20 MHz crystal:
(Clock Multiplier is bypassed)
CKP3 CKP2 CKP1 DIVISOR
SPEED
0
0
0
8
2.5Mbs
0
0
1
16
1.25Mbs
0
1
0
32
625Kbs
0
1
1
64
312.5Kbs
1
0
0
128
156.25Kbs
NOTE: The lowest data rate achievable by the COM20020I
is 156.25Kbs. Defaults to 000 or 2.5Mbs. For Clock
Multiplier output clock speed greater than 20 MHz, CKP3,
CKP2 and CKP1 must all be zero.
SLOWARB
This bit, when set, will divide the arbitration clock by 2.
Memory cycle times will increase when slow arbitration is
selected.
NOTE: For clock multiplier output clock speeds greater
than 40 MHz, SLOWARB must be set. Defaults to low.
SMSC COM20020I 3.3V
Page 33
DATASHEET
Revision 12-06-06