SI53321 Datasheet, PDF (9/28 Pages) Silicon Laboratories – 1:10 LOW JITTER LVPECL CLOCK BUFFER

Si53321
2.2. Input Bias Resistors
Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected.
The non-inverting input is biased with a 18.75 k pull-down to GND and a 75 k pull-up to V_DD. The inverting input
is biased with a 75 k pull-up to V_DD.
V_DD
R_PU
R_PU
+
R_PD
–
R_PU = 75 k
R_PD = 18.75 k
CLK0 or
CLK1
Figure 5. Input Bias Resistors
2.3. Input Mux
The Si53321 provides two clock inputs for applications that need to select between one of two clock sources. The
CLK_SEL pin selects the active clock input. The table below summarizes the input and output clock based on the
input mux and output enable pin settings.
Table 12. Input Mux Logic
CLK_SEL CLK0
CLK1
Q¹
Q
L
L
X
L
H
L
H
X
H
L
H
X
L
L
H
H
X
H
H
L
Notes:
1. On the next negative transition of CLK0 or CLK1.
Rev. 1.0
9