SI53321 Datasheet, PDF (1/28 Pages) Silicon Laboratories – 1:10 LOW JITTER LVPECL CLOCK BUFFER

Si53321
1:10 LOW JITTER LVPECL CLOCK BUFFER
WITH 2:1 INPUT MUX (<1.25 GHZ)
Features
 10 LVPECL outputs
 RoHS compliant, Pb-free
 Ultra-low additive jitter: 45 fs rms typ  32-QFN, 32-eLQFP
 Wide frequency range: dc to
 Industrial temperature range:
1.25 GHz
–40 to +85°C
 Input compatible with LVPECL,
 Footprint-compatible with
LVDS, CML, HCSL, LVCMOS
MC100LVEP111, CDCLVP111,
 2:1 input mux
 Low output-output skew: 25 ps (typ)
MAX9311, ICS853S111BI,
ICS85310-1
Applications
 High-speed clock distribution
 Ethernet switch/router
 Optical Transport Network (OTN)
 SONET/SDH
 PCI Express Gen 1/2/3
 Storage
 Telecom
 Industrial
 Servers
 Backplane clock distribution
Ordering Information:
See page 19.
Pin Assignments (Top View)
Description
The Si53321 is an ultra-low jitter ten output differential buffer. The Si53321
features a 2:1 input mux, making it ideal for redundant clocking applications. The
Si53321 utilizes Silicon Laboratories' advanced CMOS technology to fanout
clocks from dc to 1.25 GHz with guaranteed low additive jitter, low skew, and low
propagation delay variability. The Si53321 features minimal cross-talk and
provides superior supply noise rejection, simplifying low jitter clock distribution in
noisy environments.
Functional Block Diagram
32 31 30 29 28 27 26 25
VDD
1
24
Q3
CLK_SEL
2
23
Q3
CLK0
3
CLK0
4
NC
5
Exposed
GND Pad
22
Q4
21
Q4
20
Q5
CLK1
6
19
Q5
CLK1
7
18
Q6
GND
8
17
Q6
9 10 11 12 13 14 15 16
Q0
Q0
VDD
Power
Q1
Supply
Filtering
Q1
Q2
Q2
Q3
Q3
CLK0
0
Q4
CLK0
Q4
Q5
CLK1
Q5
1
CLK1
Q6
Q6
CLK_SEL
Q7
Q7
Q8
Q8
GND
Q9
Q9
32 31 30 29 28 27 26 25
VDD 1
24 Q3
CLK_SEL 2
23 Q3
CLK0 3
CLK0 4
NC ⁵
Exposed
GND Pad
22 Q4
21 Q4
20 _Q5
CLK1 6
19 Q5
CLK1 7
18 Q6
GND 8
17 Q6
9 10 11 12 13 14 15 16
Patents pending
Rev. 1.0 4/15
Copyright © 2015 by Silicon Laboratories
Si53321