SI53321 Datasheet, PDF (10/28 Pages) Silicon Laboratories – 1:10 LOW JITTER LVPECL CLOCK BUFFER

Si53321
2.4. Output Clock Termination Options
The recommended output clock termination options are shown below. Unused outputs should be left unconnected.
VDDO
DC Coupled LVPECL Termination Scheme 1
R1
R1
VDDO _{= 3.3V or 2.5V}
Si533xx
Q
50
Qn
50
3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm
2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm
R2
R2
VDD = VDDO
LVPECL
Receiver
VTERM = VDDO – 2V
R1 // R2 = 50 Ohm
DC Coupled LVPECL Termination Scheme 2
VDDO _{= 3.3V or 2.5V}
Si533xx
Q
50
Qn
50
50
VDD = VDDO
LVPECL
Receiver
50
VTERM = VDDO – 2V
VDDO
AC Coupled LVPECL Termination Scheme 1
VDDO _{= 3.3V or 2.5V}
Si533xx
Q
Qn
Rb Rb
R1
0.1 uF
50
50
0.1 uF
R2
R1
VDD _{= 3.3V or 2.5V}
LVPECL
Receiver
R2
VBIAS = VDD – 1.3V
R1 // R2 = 50 Ohm
3.3V LVPECL: R1 = 82.5 Ohm, R2 = 127 Ohm, Rb = 120 Ohm
2.5V LVPECL: R1 = 62.5 Ohm, R2 = 250 Ohm, Rb = 90 Ohm
AC Coupled LVPECL Termination Scheme 2
VDDO = 3.3V or 2.5V
Si533xx
Q
Qn
Rb Rb
0.1 uF
50
50
0.1 uF ₅₀
VDD _{= 3.3V or 2.5V}
LVPECL
Receiver
50
VBIAS = VDD – 1.3 V
3.3V LVPECL: Rb = 120 Ohm
2.5V LVPECL: Rb = 90 Ohm
Figure 6. LVPECL Output Termination
10
Rev. 1.0