SI53321 Datasheet, PDF (22/28 Pages) Silicon Laboratories – 1:10 LOW JITTER LVPECL CLOCK BUFFER

Si53321
6. PCB Land Pattern
6.1. 32-eLQFP Package Land Pattern
Figure 16. Si53321 32-eLQFP Package Land Pattern
Table 16. PCB Land Pattern
Dimension
C1
C2
D1
D2
E
X1
Y1
Min
Max
8.40
8.50
8.40
8.50
1.84
2.00
1.84
2.00
0.80 BSC
0.40
0.50
1.25
1.35
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 m minimum, all
the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all
perimeter pads.
4. A single 1.5 x 1.5 mm stencil aperture should be used for the center
ground pad to achieve between 50-60% solder coverage.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
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Rev. 1.0