SI53321 Datasheet, PDF (17/28 Pages) Silicon Laboratories – 1:10 LOW JITTER LVPECL CLOCK BUFFER

Si53321
Table 13. Si53321 32-eLQFP and 32-QFN Pin Descriptions
Pin #
1
Name
V_DD
2 CLK_SEL
3
CLK0
Type*
P
I
I
Description
Core voltage supply.
Bypass with 1.0 F capacitor and place as close to the V_DD pin as possible.
Mux input select pin (LVCMOS).
When CLK_SEL is high, CLK1 is selected.
When CLK_SEL is low, CLK0 is selected.
CLK_SEL contains an internal pull-down resistor.
Input clock 0.
4
CLK0
5
NC
I Input clock 0 (complement)
When CLK0 is driven by a single-ended input, connect CLK0 to an appropriate
bias voltage (e.g., for a CMOS input apply V_DD/2).
No connect. Leave this pin unconnected.
6
CLK1
I Input clock 1.
7
CLK1
I Input clock 1 (complement)
When CLK1 is driven by a single-ended input, connect CLK1 to an appropriate
bias voltage (e.g., for a CMOS input apply V_DD/2).
8
GND
GND Ground.
9
V_DD
10
Q9
P Core voltage supply.
Bypass with 1.0 µF capacitor and place as close to the V_DD pin as possible.
O Output clock 9 (complement).
11
Q9
O Output clock 9.
12
Q8
O Output clock 8 (complement).
13
Q8
O Output clock 8.
14
Q7
O Output clock 7 (complement).
15
Q7
O Output clock 7.
16
V_DD
17
Q6
P Core voltage supply.
Bypass with 1.0 µF capacitor and place as close to the V_DD pin as possible.
O Output clock 6 (complement).
18
Q6
O Output clock 6.
19
Q5
O Output clock 5 (complement).
20
Q5
O Output clock 5.
21
Q4
O Output clock 4 (complement).
22
Q4
O Output clock 4.
23
Q3
O Output clock 3 (complement).
Rev. 1.0
17