SI5323 Datasheet, PDF (9/16 Pages) Silicon Laboratories – PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Pin #
16
17
Pin Name
CKIN1+
CKIN1–
18
LOL
19
DEC
20
INC
21
CS_CA
Si5323
Table 3. Si5323 Pin Descriptions (Continued)
I/O Signal Level
Description
I
Multi
Clock Input 1.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table of
values. The same frequency must be applied to CKIN1 and
CKIN2.
O
LVCMOS PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indica-
tor.
0 = PLL locked
1 = PLL unlocked
I
LVCMOS Latency Decrement.
A pulse on this pin decreases the input to output device
latency by 1/f_OSC (approximately 200 ps). There is no limit on
the range of latency adjustment by this method. If both INC
and DEC are tied high, phase buildout is disabled and the
device maintains a fixed-phase relationship between the
selected input clock and the output clock during an input
clock transition. Detailed operations and timing characteris-
tics for this pin may be found in the Any-Rate Precision Clock
Family Reference Manual.
This pin has a weak pull-down.
I
LVCMOS Latency Increment.
A pulse on this pin increases the input to output device
latency by 1/f_OSC (approximately 200 ps). There is no limit on
the range of latency adjustment by this method. If both INC
and DEC are tied high, phase buildout is disabled and the
device maintains a fixed-phase relationship between the
selected input clock and the output clock during an input
clock transition. Detailed operations and timing characteris-
tics for this pin may be found in the Any-Rate Precision Clock
Family Reference Manual.
This pin has a weak pull-down.
I/O LVCMOS Input Clock Select/Active Clock Indicator.
If manual clock selection mode is chosen (AUTOSEL = L),
this pin functions as the manual input clock selector. This
input is internally deglitched to prevent inadvertent clock
switching during changes in the CS input state.
0 = Select CKIN1
1 = Select CKIN2
If automatic clock selection mode is chosen (AUTOSEL = M
or H), this pin indicates which of the two input clocks is cur-
rently the active clock. If alarms exist on both CKIN1 and
CKIN2, indicating that the digital hold state has been
entered, CA will indicate the last active clock that was used
before entering the hold state.
0 = CKIN1 active input clock
1 = CKIN2 active input clock
Preliminary Rev. 0.2
9